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| author | David Shah <dave@ds0.me> | 2021-01-28 16:10:22 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-28 16:10:22 +0000 |
| commit | 15b2852b916c1299dfc1d91a217de3060701bfbe (patch) | |
| tree | 8e7ffbce4b7d253f05d0bb58ea6430aae8e1b065 /ice40/arch.h | |
| parent | 0d9790421699a22fc6a5962b41910c3b7d089353 (diff) | |
| parent | 94e8847d674388c3c8ac663fa4912bb8029b2951 (diff) | |
| download | nextpnr-15b2852b916c1299dfc1d91a217de3060701bfbe.tar.gz nextpnr-15b2852b916c1299dfc1d91a217de3060701bfbe.tar.bz2 nextpnr-15b2852b916c1299dfc1d91a217de3060701bfbe.zip | |
Merge pull request #556 from YosysHQ/dave/cleanup
General opportunistic cleanup
Diffstat (limited to 'ice40/arch.h')
| -rw-r--r-- | ice40/arch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index 1de39c33..fbf26e78 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -833,7 +833,7 @@ struct Arch : BaseCtx bool logicCellsCompatible(const CellInfo **it, const size_t size) const; // ------------------------------------------------- - // Assign architecure-specific arguments to nets and cells, which must be + // Assign architecture-specific arguments to nets and cells, which must be // called between packing or further // netlist modifications, and validity checks void assignArchInfo(); |