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| author | YRabbit <rabbit@yrabbit.cyou> | 2022-05-27 22:44:21 +1000 |
|---|---|---|
| committer | YRabbit <rabbit@yrabbit.cyou> | 2022-05-27 22:44:21 +1000 |
| commit | db696af2fe53ab4dc341a09303bb6cd371d76519 (patch) | |
| tree | 04c7ffcc0bdda09aec357f7d739e598b07252ad6 /gowin/constids.inc | |
| parent | 4ecbf6c6e941699413e0d0bba660fc9dc18efcfe (diff) | |
| download | nextpnr-db696af2fe53ab4dc341a09303bb6cd371d76519.tar.gz nextpnr-db696af2fe53ab4dc341a09303bb6cd371d76519.tar.bz2 nextpnr-db696af2fe53ab4dc341a09303bb6cd371d76519.zip | |
gowin: Add support for long wires
Gowin chips have a highly sophisticated system of long wires that are
wired to each cell and allow the clock or logic to spread quickly.
This commit implements some of the capabilities of the long wire system
for quadrants, leaving out the fine-tuning of them for each column.
To make use of the long wire system, the specified wire is cut at the
driver and a special cell is placed between the driver and the rest of
the wire.
* VCC and GND can not use long wires because they are in every cell and
there is no point in using a net
* Long wire numbers can be specified manually or assigned automatically.
* The route from the driver to the port of the new cell can be quite
long, this will have to be solved somehow.
* It might make sense to add a mechanism for automatically finding
candidates for long wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Diffstat (limited to 'gowin/constids.inc')
| -rw-r--r-- | gowin/constids.inc | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/gowin/constids.inc b/gowin/constids.inc index 3691c506..99c791f8 100644 --- a/gowin/constids.inc +++ b/gowin/constids.inc @@ -679,6 +679,81 @@ X(IOBHS) X(IOBIS) X(IOBJS) +// long wires +X(BUFS) +X(BUFS0) +X(BUFS1) +X(BUFS2) +X(BUFS3) +X(BUFS4) +X(BUFS5) +X(BUFS6) +X(BUFS7) +X(LWT0) +X(LWB0) +X(LWT1) +X(LWB1) +X(LWT2) +X(LWB2) +X(LWT3) +X(LWB3) +X(LWT4) +X(LWB4) +X(LWT5) +X(LWB5) +X(LWT6) +X(LWB6) +X(LWT7) +X(LWB7) +X(LWSPINETL0) +X(LWSPINETL1) +X(LWSPINETL2) +X(LWSPINETL3) +X(LWSPINETL4) +X(LWSPINETL5) +X(LWSPINETL6) +X(LWSPINETL7) +X(LWSPINETR0) +X(LWSPINETR1) +X(LWSPINETR2) +X(LWSPINETR3) +X(LWSPINETR4) +X(LWSPINETR5) +X(LWSPINETR6) +X(LWSPINETR7) +X(LWSPINEBL0) +X(LWSPINEBL1) +X(LWSPINEBL2) +X(LWSPINEBL3) +X(LWSPINEBL4) +X(LWSPINEBL5) +X(LWSPINEBL6) +X(LWSPINEBL7) +X(LWSPINEBR0) +X(LWSPINEBR1) +X(LWSPINEBR2) +X(LWSPINEBR3) +X(LWSPINEBR4) +X(LWSPINEBR5) +X(LWSPINEBR6) +X(LWSPINEBR7) +X(LWI0) +X(LWI1) +X(LWI2) +X(LWI3) +X(LWI4) +X(LWI5) +X(LWI6) +X(LWI7) +X(LWO0) +X(LWO1) +X(LWO2) +X(LWO3) +X(LWO4) +X(LWO5) +X(LWO6) +X(LWO7) + // IOLOGIC X(TX) X(XXX_VSS) @@ -812,6 +887,11 @@ X(CENT_SPINE_PCLK) X(SPINE_TAP_PCLK) X(TAP_BRANCH_PCLK) X(BRANCH_PCLK) +X(CENT_SPINE_SCLK) +X(SPINE_TAP_SCLK_0) +X(SPINE_TAP_SCLK_1) +X(TAP_BRANCH_SCLK) +X(BRANCH_SCLK) X(clksetpos) X(clkholdpos) X(clk_qpos) |