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authorYRabbit <rabbit@yrabbit.cyou>2022-07-19 18:51:25 +1000
committerYRabbit <rabbit@yrabbit.cyou>2022-07-19 18:51:25 +1000
commit6969782a4b76dd7846bb206d08768736b9cac341 (patch)
tree44ffd30ab8437868b353a868d80606c7699a01c1 /gowin/cells.cc
parent5667113f8a8f23cf0385a3e0ae88cd844e622443 (diff)
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gowin: Remove incomprehensible names of the muxes
There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Diffstat (limited to 'gowin/cells.cc')
-rw-r--r--gowin/cells.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/gowin/cells.cc b/gowin/cells.cc
index d83b07c8..0c027d38 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -56,8 +56,8 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
new_cell->addInput(id_CLK);
new_cell->addInput(id_CE);
new_cell->addInput(id_LSR);
- } else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
- type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
+ } else if (type == id_MUX2_LUT5 || type == id_MUX2_LUT6 || type == id_MUX2_LUT7 || type == id_MUX2_LUT7 ||
+ type == id_MUX2_LUT8) {
new_cell->addInput(id_I0);
new_cell->addInput(id_I1);
new_cell->addInput(id_SEL);
@@ -190,7 +190,7 @@ void sram_to_ramw_split(Context *ctx, CellInfo *ram, CellInfo *ramw)
ram->movePortTo(ctx->id("DI[1]"), ramw, id_B5);
ram->movePortTo(ctx->id("DI[2]"), ramw, id_C5);
ram->movePortTo(ctx->id("DI[3]"), ramw, id_D5);
-
+
ram->movePortTo(ctx->id("CLK"), ramw, id_CLK);
ram->movePortTo(ctx->id("WRE"), ramw, id_LSR);
}