Add stub generator API to generic arch

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2 files changed, 52 insertions, 6 deletions

diff --git a/generic/arch.cc b/generic/arch.cc
index 9bdda5ba..0e4a3365 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -24,8 +24,6 @@ NEXTPNR_NAMESPACE_BEGIN
 
 Arch::Arch(ArchArgs) {}
 
-std::string Arch::getChipName() { return "Generic"; }
-
 void IdString::initialize_arch(const BaseCtx *ctx) {}
 
 // ---------------------------------------------------------------
diff --git a/generic/arch.h b/generic/arch.h
index ae68b974..4280951c 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -27,14 +27,62 @@ struct ArchArgs
 {
 };
 
+struct WireInfo;
+
+struct PipInfo
+{
+    IdString name, bound_net;
+    WireInfo *srcWire, *dstWire;
+    DelayInfo delay;
+    std::vector<GraphicElement> graphics;
+};
+
+struct WireInfo
+{
+    IdString name, bound_net;
+    std::vector<GraphicElement> graphics;
+    std::vector<PipInfo*> downhill, uphill, aliases;
+};
+
+struct PinInfo
+{
+    IdString name;
+    WireInfo *wire;
+    PortType type;
+};
+
+struct BelInfo
+{
+    IdString name, type, bound_cell;
+    std::unordered_map<IdString, PinInfo> pins;
+    std::vector<GraphicElement> graphics;
+};
+
 struct Arch : BaseCtx
 {
-    Arch(ArchArgs args);
+    std::string chipName;
+
+    std::unordered_map<IdString, WireInfo> wires;
+    std::unordered_map<IdString, PipInfo> pips;
+    std::unordered_map<IdString, BelInfo> bels;
 
-    std::string getChipName();
+    std::vector<IdString> bel_ids, wire_ids, pip_ids;
+    std::unordered_map<IdString, std::vector<IdString>> bel_ids_by_type;
+
+    void addWire(IdString name);
+    void addPip(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
+    void addAias(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
+
+    void addBel(IdString name, IdString type);
+    void addBelInput(IdString cell, IdString name, IdString wire);
+    void addBwlOutput(IdString cell, IdString name, IdString wire);
+    void addBelInout(IdString cell, IdString name, IdString wire);
+
+    // ---------------------------------------------------------------
+
+    Arch(ArchArgs args);
 
-    virtual IdString id(const std::string &s) const { abort(); }
-    virtual IdString id(const char *s) const { abort(); }
+    std::string getChipName() { return chipName; }
 
     IdString archId() const { return id("generic"); }
     IdString archArgsToId(ArchArgs args) const { return id("none"); }