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authorDavid Shah <dave@ds0.me>2020-10-15 09:36:15 +0100
committerDavid Shah <dave@ds0.me>2020-10-15 09:36:15 +0100
commitb18ea204c2cd88a5fad8989f4597cfa3a8152ca1 (patch)
tree83d380897bc119f7f4295a8f795e23a826e62735 /generic
parent576baa994f4b9e1746a231469bfd9e65d1d5a2b4 (diff)
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Remove wire alias API
It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'generic')
-rw-r--r--generic/arch.cc16
-rw-r--r--generic/arch.h4
-rw-r--r--generic/arch_pybindings.cc8
3 files changed, 2 insertions, 26 deletions
diff --git a/generic/arch.cc b/generic/arch.cc
index 6979673a..4bf337bd 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -90,20 +90,6 @@ void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWi
tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
}
-void Arch::addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay)
-{
- NPNR_ASSERT(pips.count(name) == 0);
- PipInfo &pi = pips[name];
- pi.name = name;
- pi.type = type;
- pi.srcWire = srcWire;
- pi.dstWire = dstWire;
- pi.delay = delay;
-
- wire_info(srcWire).aliases.push_back(name);
- pip_ids.push_back(name);
-}
-
void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
{
NPNR_ASSERT(bels.count(name) == 0);
@@ -467,8 +453,6 @@ const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return wire
const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wires.at(wire).uphill; }
-const std::vector<PipId> &Arch::getWireAliases(WireId wire) const { return wires.at(wire).aliases; }
-
// ---------------------------------------------------------------
GroupId Arch::getGroupByName(IdString name) const { return name; }
diff --git a/generic/arch.h b/generic/arch.h
index cbfb943d..011d7d45 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -50,7 +50,7 @@ struct WireInfo
IdString name, type;
std::map<IdString, std::string> attrs;
NetInfo *bound_net;
- std::vector<PipId> downhill, uphill, aliases;
+ std::vector<PipId> downhill, uphill;
BelPin uphill_bel_pin;
std::vector<BelPin> downhill_bel_pins;
std::vector<BelPin> bel_pins;
@@ -142,7 +142,6 @@ struct Arch : BaseCtx
void addWire(IdString name, IdString type, int x, int y);
void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
- void addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay);
void addBel(IdString name, IdString type, Loc loc, bool gb);
void addBelInput(IdString bel, IdString name, IdString wire);
@@ -241,7 +240,6 @@ struct Arch : BaseCtx
DelayInfo getPipDelay(PipId pip) const;
const std::vector<PipId> &getPipsDownhill(WireId wire) const;
const std::vector<PipId> &getPipsUphill(WireId wire) const;
- const std::vector<PipId> &getWireAliases(WireId wire) const;
GroupId getGroupByName(IdString name) const;
IdString getGroupName(GroupId group) const;
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index c00686dd..7f7229fd 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -120,8 +120,6 @@ void arch_wrap_python(py::module &m)
"getPipsDownhill");
fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill,
wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill");
- fn_wrapper_1a<Context, decltype(&Context::getWireAliases), &Context::getWireAliases,
- wrap_context<const std::vector<PipId> &>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireAliases");
fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>,
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire");
@@ -162,10 +160,6 @@ void arch_wrap_python(py::module &m)
conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>, pass_through<DelayInfo>,
pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, "srcWire"_a, "dstWire"_a,
"delay"_a, "loc"_a);
- fn_wrapper_5a_v<Context, decltype(&Context::addAlias), &Context::addAlias, conv_from_str<IdString>,
- conv_from_str<IdString>, conv_from_str<IdString>, conv_from_str<IdString>,
- pass_through<DelayInfo>>::def_wrap(ctx_cls, "addAlias", "name"_a, "type"_a, "srcWire"_a,
- "dstWire"_a, "delay"_a);
fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdString>,
conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
@@ -240,4 +234,4 @@ void arch_wrap_python(py::module &m)
NEXTPNR_NAMESPACE_END
-#endif \ No newline at end of file
+#endif