Add getBelHidden and add some missing "override" statements.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

4 files changed, 12 insertions, 8 deletions

diff --git a/generic/arch.cc b/generic/arch.cc
index 912f8a53..b54a8b65 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -91,7 +91,7 @@ void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStri
     tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
 }
 
-void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb)
+void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden)
 {
     NPNR_ASSERT(bels.count(name) == 0);
     NPNR_ASSERT(bel_by_loc.count(loc) == 0);
@@ -102,6 +102,7 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb)
     bi.y = loc.y;
     bi.z = loc.z;
     bi.gb = gb;
+    bi.hidden = hidden;
 
     bel_ids.push_back(name);
     bel_by_loc[loc] = name;
@@ -319,6 +320,8 @@ const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
 
 IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
 
+bool Arch::getBelHidden(BelId bel) const { return bels.at(bel).hidden; }
+
 const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; }
 
 WireId Arch::getBelPinWire(BelId bel, IdString pin) const
diff --git a/generic/arch.h b/generic/arch.h
index 09fd8e34..accf2dce 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -77,6 +77,7 @@ struct BelInfo
     DecalXY decalxy;
     int x, y, z;
     bool gb;
+    bool hidden;
 };
 
 struct GroupInfo
@@ -177,7 +178,7 @@ struct Arch : ArchAPI<ArchRanges>
     void addWire(IdStringList name, IdString type, int x, int y);
     void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, Loc loc);
 
-    void addBel(IdStringList name, IdString type, Loc loc, bool gb);
+    void addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
     void addBelInput(IdStringList bel, IdString name, IdStringList wire);
     void addBelOutput(IdStringList bel, IdString name, IdStringList wire);
     void addBelInout(IdStringList bel, IdString name, IdStringList wire);
@@ -237,6 +238,7 @@ struct Arch : ArchAPI<ArchRanges>
     CellInfo *getConflictingBelCell(BelId bel) const override;
     const std::vector<BelId> &getBels() const override;
     IdString getBelType(BelId bel) const override;
+    bool getBelHidden(BelId bel) const override;
     const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
     WireId getBelPinWire(BelId bel, IdString pin) const override;
     PortType getBelPinType(BelId bel, IdString pin) const override;
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index 29e8bc53..3dc04206 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -162,10 +162,9 @@ void arch_wrap_python(py::module &m)
                     pass_through<DelayInfo>, pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a,
                                                                           "srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a);
 
-    fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
-                    conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
-                                                                                              "name"_a, "type"_a,
-                                                                                              "loc"_a, "gb"_a);
+    fn_wrapper_5a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
+                    conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>,
+                    pass_through<bool>>::def_wrap(ctx_cls, "addBel", "name"_a, "type"_a, "loc"_a, "gb"_a, "hidden"_a);
     fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdStringList>,
                     conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
                                                                                     "name"_a, "wire"_a);
diff --git a/generic/examples/simple.py b/generic/examples/simple.py
index 9379b505..4b7f4025 100644
--- a/generic/examples/simple.py
+++ b/generic/examples/simple.py
@@ -20,13 +20,13 @@ for x in range(X):
 			if x == y:
 				continue
 			for z in range(2):
-				ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False)
+				ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False, hidden=False)
 				ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z))
 				ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z))
 				ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z))
 		else:
 			for z in range(N):
-				ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False)
+				ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False, hidden=False)
 				ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z))
 				for k in range(K):
 					ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k))