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author | David Shah <davey1576@gmail.com> | 2019-04-19 17:40:55 +0100 |
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committer | GitHub <noreply@github.com> | 2019-04-19 17:40:55 +0100 |
commit | 5344bc3b65f4e06f983db781e9a82d30b3f1512b (patch) | |
tree | 5f794074ccc963a9dbf756558e34a8eba0d5fa26 /generic/synth | |
parent | 0be844e6a8d0a36a50815ec5331fd7480dd20db6 (diff) | |
parent | 87a24460813b9f52189323352554a1c352836ee2 (diff) | |
download | nextpnr-5344bc3b65f4e06f983db781e9a82d30b3f1512b.tar.gz nextpnr-5344bc3b65f4e06f983db781e9a82d30b3f1512b.tar.bz2 nextpnr-5344bc3b65f4e06f983db781e9a82d30b3f1512b.zip |
Merge pull request #261 from YosysHQ/pygeneric
Python API for generic architecture
Diffstat (limited to 'generic/synth')
-rw-r--r-- | generic/synth/cells_map.v | 10 | ||||
-rw-r--r-- | generic/synth/prims.v | 59 | ||||
-rw-r--r-- | generic/synth/synth_generic.tcl | 24 |
3 files changed, 93 insertions, 0 deletions
diff --git a/generic/synth/cells_map.v b/generic/synth/cells_map.v new file mode 100644 index 00000000..a6027534 --- /dev/null +++ b/generic/synth/cells_map.v @@ -0,0 +1,10 @@ +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + input [WIDTH-1:0] A; + output Y; + + LUT #(.K(`LUT_K), .INIT(LUT)) _TECHMAP_REPLACE_ (.I(A), .Q(Y)); +endmodule + +module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule diff --git a/generic/synth/prims.v b/generic/synth/prims.v new file mode 100644 index 00000000..95fcfac7 --- /dev/null +++ b/generic/synth/prims.v @@ -0,0 +1,59 @@ +// LUT and DFF are combined to a GENERIC_SLICE + +module LUT #( + parameter K = 4, + parameter [2**K-1:0] INIT = 0, +) ( + input [K-1:0] I, + output Q +); + assign Q = INIT[I]; +endmodule + +module DFF ( + input CLK, D, + output reg Q +); + always @(posedge CLK) + Q <= D; +endmodule + +module GENERIC_SLICE #( + parameter K = 4, + parameter [2**K-1:0] INIT = 0, + parameter FF_USED = 1'b0 +) ( + input CLK, + input [K-1:0] I, + output Q +); + + wire lut_q; + LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q)); + + generate if (FF_USED) + DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q)); + else + assign Q = lut_q; + endgenerate +endmodule + +module GENERIC_IOB #( + parameter INPUT_USED = 1'b0, + parameter OUTPUT_USED = 1'b0, + parameter ENABLE_USED = 1'b0 +) ( + inout PAD, + input I, EN, + output O +); + generate if (OUTPUT_USED && ENABLE_USED) + assign PAD = EN ? I : 1'bz; + else if (OUTPUT_USED) + assign PAD = I; + endgenerate + + generate if (INPUT_USED) + assign O = PAD; + endgenerate +endmodule
\ No newline at end of file diff --git a/generic/synth/synth_generic.tcl b/generic/synth/synth_generic.tcl new file mode 100644 index 00000000..e5d88e0d --- /dev/null +++ b/generic/synth/synth_generic.tcl @@ -0,0 +1,24 @@ +# Usage +# tcl synth_generic.tcl {K} {out.json} + +set LUT_K 4 +if {$argc > 0} { set LUT_K [lindex $argv 0] } +yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v +yosys hierarchy -check +yosys proc +yosys flatten +yosys tribuf -logic +yosys deminout +yosys synth -run coarse +yosys memory_map +yosys opt -full +yosys techmap -map +/techmap.v +yosys opt -fast +yosys abc -lut $LUT_K -dress +yosys clean +yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v +yosys clean +yosys hierarchy -check +yosys stat + +if {$argc > 1} { yosys write_json [lindex $argv 1] } |