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author | David Shah <dave@ds0.me> | 2019-11-27 15:17:53 +0000 |
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committer | David Shah <dave@ds0.me> | 2019-11-27 15:17:53 +0000 |
commit | 2f56b989598def4682b29ccfe3bbe6f540e4e12a (patch) | |
tree | f6b1878164c1341511b69872bdabd32ed2ccf8f0 /generic/synth/prims.v | |
parent | 6562edc98e212516f466a70e949c71b2d48cc75d (diff) | |
download | nextpnr-2f56b989598def4682b29ccfe3bbe6f540e4e12a.tar.gz nextpnr-2f56b989598def4682b29ccfe3bbe6f540e4e12a.tar.bz2 nextpnr-2f56b989598def4682b29ccfe3bbe6f540e4e12a.zip |
generic: Add support for post-PnR simulation
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'generic/synth/prims.v')
-rw-r--r-- | generic/synth/prims.v | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/generic/synth/prims.v b/generic/synth/prims.v index 1148041c..ca445e6e 100644 --- a/generic/synth/prims.v +++ b/generic/synth/prims.v @@ -2,18 +2,27 @@ module LUT #( parameter K = 4, - parameter [2**K-1:0] INIT = 0, + parameter [2**K-1:0] INIT = 0 ) ( input [K-1:0] I, output Q ); - assign Q = INIT[I]; + wire [K-1:0] I_pd; + + genvar ii; + generate + for (ii = 0; ii < K; ii = ii + 1'b1) + assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii]; + endgenerate + + assign Q = INIT[I_pd]; endmodule module DFF ( input CLK, D, output reg Q ); + initial Q = 1'b0; always @(posedge CLK) Q <= D; endmodule |