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authorDavid Shah <dave@ds0.me>2019-08-07 10:40:25 +0100
committerGitHub <noreply@github.com>2019-08-07 10:40:25 +0100
commiteaef3b600e2e8c4633db25edd4ad017b59a1cc79 (patch)
tree66a6e88614d99dfdf8c15ac3a1d1a13339784f9c /generic/examples
parent1ecf271cb32f9f78ea082788c6534f2523144d01 (diff)
parent8eef6ac55e48aa181d1e268fcec004a58f9d8db4 (diff)
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Merge pull request #306 from YosysHQ/dave/jsonfix
Major improvements to constants/Property
Diffstat (limited to 'generic/examples')
-rw-r--r--generic/examples/simple_timing.py2
-rw-r--r--generic/examples/write_fasm.py3
2 files changed, 2 insertions, 3 deletions
diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py
index a955c8d7..2ccb197e 100644
--- a/generic/examples/simple_timing.py
+++ b/generic/examples/simple_timing.py
@@ -4,7 +4,7 @@ for cname, cell in ctx.cells:
if cname in ("$PACKER_GND", "$PACKER_VCC"):
continue
K = int(cell.params["K"])
- if cell.params["FF_USED"] == "1":
+ if int(cell.params["FF_USED"], 2) == 1:
ctx.addCellTimingClock(cell=cname, port="CLK")
for i in range(K):
ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK",
diff --git a/generic/examples/write_fasm.py b/generic/examples/write_fasm.py
index 1f279b63..ede8f16b 100644
--- a/generic/examples/write_fasm.py
+++ b/generic/examples/write_fasm.py
@@ -45,8 +45,7 @@ def write_fasm(ctx, paramCfg, f):
print("%s.%s" % (cell.bel, fasm_name), file=f)
else:
# Parameters with width >32 are direct binary, otherwise denary
- binval = val if cfg.width > 32 else "{:0{}b}".format(int(val), cfg.width)
- print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, binval), file=f)
+ print("%s.%s[%d:0] = %d'b%s" % (cell.bel, fasm_name, cfg.width-1, cfg.width, val), file=f)
else:
print("%s.%s.%s" % (cell.bel, fasm_name, val), file=f)
print("", file=f) \ No newline at end of file