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authorgatecat <gatecat@ds0.me>2022-08-04 10:55:19 +0200
committergatecat <gatecat@ds0.me>2022-08-04 10:55:19 +0200
commit37f0886cb9e949cb49250f973a852c816b5ab892 (patch)
tree95604b304192f63c6d2f3753e21568ba4596f7d1 /generic/arch.cc
parent1b54fa2a1c1fae82315916f3b92f6282f376c861 (diff)
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generic: addBelPin with direction as an arg
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'generic/arch.cc')
-rw-r--r--generic/arch.cc30
1 files changed, 5 insertions, 25 deletions
diff --git a/generic/arch.cc b/generic/arch.cc
index 3df58c9b..9992e1cd 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -134,40 +134,20 @@ BelId Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidd
return bel;
}
-void Arch::addBelInput(BelId bel, IdString name, WireId wire)
-{
- auto &bi = bel_info(bel);
- NPNR_ASSERT(bi.pins.count(name) == 0);
- PinInfo &pi = bi.pins[name];
- pi.name = name;
- pi.wire = wire;
- pi.type = PORT_IN;
-
- if (wire != WireId())
- wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
+void Arch::addBelInput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_IN); }
-void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
-{
- auto &bi = bel_info(bel);
- NPNR_ASSERT(bi.pins.count(name) == 0);
- PinInfo &pi = bi.pins[name];
- pi.name = name;
- pi.wire = wire;
- pi.type = PORT_OUT;
+void Arch::addBelOutput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_OUT); }
- if (wire != WireId())
- wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
+void Arch::addBelInout(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_INOUT); }
-void Arch::addBelInout(BelId bel, IdString name, WireId wire)
+void Arch::addBelPin(BelId bel, IdString name, WireId wire, PortType type)
{
auto &bi = bel_info(bel);
NPNR_ASSERT(bi.pins.count(name) == 0);
PinInfo &pi = bi.pins[name];
pi.name = name;
pi.wire = wire;
- pi.type = PORT_INOUT;
+ pi.type = type;
if (wire != WireId())
wire_info(wire).bel_pins.push_back(BelPin{bel, name});