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authorgatecat <gatecat@ds0.me>2021-02-25 16:16:37 +0000
committerGitHub <noreply@github.com>2021-02-25 16:16:37 +0000
commitde107da5b3c66d329de0a0430a67ca843e27f3bd (patch)
treee18884eb5006aa991402b3576e188d7977ef88e8 /fpga_interchange
parentab8dfcfba4544c6733d074b24b0529d431b66d29 (diff)
parent23413a4d12ad070c8a356c5a3186f81def705c54 (diff)
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Merge pull request #598 from YosysHQ/gatecat/compiler-flags
Tighten up compiler flags
Diffstat (limited to 'fpga_interchange')
-rw-r--r--fpga_interchange/dedicated_interconnect.cc4
-rw-r--r--fpga_interchange/fpga_interchange.cpp2
2 files changed, 3 insertions, 3 deletions
diff --git a/fpga_interchange/dedicated_interconnect.cc b/fpga_interchange/dedicated_interconnect.cc
index 820896a3..988b13ab 100644
--- a/fpga_interchange/dedicated_interconnect.cc
+++ b/fpga_interchange/dedicated_interconnect.cc
@@ -441,7 +441,7 @@ void DedicatedInterconnect::find_dedicated_interconnect()
continue;
}
- for (size_t i = 0; i < bel_data.num_bel_wires; ++i) {
+ for (int i = 0; i < bel_data.num_bel_wires; ++i) {
if (bel_data.types[i] != PORT_IN) {
continue;
}
@@ -470,7 +470,7 @@ void DedicatedInterconnect::find_dedicated_interconnect()
continue;
}
- for (size_t i = 0; i < bel_data.num_bel_wires; ++i) {
+ for (int i = 0; i < bel_data.num_bel_wires; ++i) {
if (bel_data.types[i] != PORT_OUT) {
continue;
}
diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp
index a1642789..9410b117 100644
--- a/fpga_interchange/fpga_interchange.cpp
+++ b/fpga_interchange/fpga_interchange.cpp
@@ -1018,7 +1018,7 @@ size_t ModuleReader::translate_port_index(LogicalNetlist::Netlist::PortInstance:
NPNR_ASSERT(port.isBus());
uint32_t idx = port_inst.getBusIdx().getIdx();
size_t width = get_port_width(port);
- NPNR_ASSERT(idx >= 0 && idx < width);
+ NPNR_ASSERT(idx < width);
return width - 1 - idx;
}
}