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| author | gatecat <gatecat@ds0.me> | 2021-04-30 13:29:21 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-30 13:29:21 +0100 |
| commit | 0461cc8c3ac93bc525d35a15528c4711f244b9c6 (patch) | |
| tree | 240de8f8603237a782a34df3a18915c495a394b3 /fpga_interchange | |
| parent | d718ccaa78763300146f0b8e5f2339b7fba97542 (diff) | |
| parent | 5225550b5b83db2685f6c3ad3ce73e1eaadea891 (diff) | |
| download | nextpnr-0461cc8c3ac93bc525d35a15528c4711f244b9c6.tar.gz nextpnr-0461cc8c3ac93bc525d35a15528c4711f244b9c6.tar.bz2 nextpnr-0461cc8c3ac93bc525d35a15528c4711f244b9c6.zip | |
Merge pull request #690 from YosysHQ/gatecat/interchange-wire-types
interchange: Add wire types
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch.cc | 19 | ||||
| -rw-r--r-- | fpga_interchange/chipdb.h | 18 |
2 files changed, 35 insertions, 2 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 441c2e1f..c49a172b 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -461,7 +461,24 @@ WireId Arch::getWireByName(IdStringList name) const return ret; } -IdString Arch::getWireType(WireId wire) const { return id(""); } +IdString Arch::getWireType(WireId wire) const +{ + int tile = wire.tile, index = wire.index; + if (tile == -1) { + // Nodal wire + const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0]; + tile = wr.tile; + index = wr.index; + } + auto &w2t = chip_info->tiles[tile].tile_wire_to_type; + if (index >= w2t.ssize()) + return IdString(); + int wire_type = w2t[index]; + if (wire_type == -1) + return IdString(); + return IdString(chip_info->wire_types[wire_type].name); +} + std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; } // ----------------------------------------------------------------------- diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index b66640e3..e9cac84e 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN * kExpectedChipInfoVersion */ -static constexpr int32_t kExpectedChipInfoVersion = 7; +static constexpr int32_t kExpectedChipInfoVersion = 8; // Flattened site indexing. // @@ -182,6 +182,9 @@ NPNR_PACKED_STRUCT(struct TileInstInfoPOD { // as they will never be nodal // -1 if a tile-local wire; node index if nodal wire RelSlice<int32_t> tile_wire_to_node; + + // Index into wire_types + RelSlice<int16_t> tile_wire_to_type; }); NPNR_PACKED_STRUCT(struct TileWireRefPOD { @@ -305,6 +308,18 @@ NPNR_PACKED_STRUCT(struct ConstantsPOD { RelSlice<DefaultCellConnsPOD> default_conns; }); +enum WireCategory +{ + WIRE_CAT_GENERAL = 0, + WIRE_CAT_SPECIAL = 1, + WIRE_CAT_GLOBAL = 2, +}; + +NPNR_PACKED_STRUCT(struct WireTypePOD { + int32_t name; // constid + int32_t category; // WireCategory +}); + NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelPtr<char> name; RelPtr<char> generator; @@ -317,6 +332,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD { RelSlice<TileInstInfoPOD> tiles; RelSlice<NodeInfoPOD> nodes; RelSlice<PackagePOD> packages; + RelSlice<WireTypePOD> wire_types; // BEL bucket constids. RelSlice<int32_t> bel_buckets; |