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authorAlessandro Comodi <acomodi@antmicro.com>2021-06-02 09:49:30 +0200
committerAlessandro Comodi <acomodi@antmicro.com>2021-06-11 11:19:01 +0200
commit104536b7aae5970ae1d1e95394f26fbf04603d12 (patch)
tree0f1fad9a952f272e6436456077fe54ba3a7730ea /fpga_interchange/site_routing_cache.h
parent7278d3c0edbc6f92ef4c69d7c5db66e811c7e9c4 (diff)
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interchange: add support for generating BEL clusters
Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/site_routing_cache.h')
-rw-r--r--fpga_interchange/site_routing_cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/site_routing_cache.h b/fpga_interchange/site_routing_cache.h
index b4baf65a..a430d206 100644
--- a/fpga_interchange/site_routing_cache.h
+++ b/fpga_interchange/site_routing_cache.h
@@ -32,7 +32,7 @@ struct SiteRoutingSolution
{
void store_solution(const SiteArch *ctx, const RouteNodeStorage *node_storage, const SiteWire &driver,
std::vector<size_t> solutions);
- void verify(const SiteArch *ctx, const SiteNetInfo &net);
+ bool verify(const SiteArch *ctx, const SiteNetInfo &net);
void clear()
{