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authorMaciej Kurc <mkurc@antmicro.com>2021-07-16 13:28:40 +0200
committerMaciej Kurc <mkurc@antmicro.com>2021-07-16 13:28:40 +0200
commit044c9ba2d4e66cf34214fdfd62fb90a872da64b1 (patch)
tree4d8bd1f21274a426df6d951f5546f524edf3c740 /fpga_interchange/site_lut_mapping_cache.h
parentd52516756cf32ecb53b75e8a6f032ebeeb427a71 (diff)
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LUT mapping cache optimizations 1
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'fpga_interchange/site_lut_mapping_cache.h')
-rw-r--r--fpga_interchange/site_lut_mapping_cache.h52
1 files changed, 26 insertions, 26 deletions
diff --git a/fpga_interchange/site_lut_mapping_cache.h b/fpga_interchange/site_lut_mapping_cache.h
index 4a81711f..b07e3e77 100644
--- a/fpga_interchange/site_lut_mapping_cache.h
+++ b/fpga_interchange/site_lut_mapping_cache.h
@@ -28,6 +28,11 @@ NEXTPNR_NAMESPACE_BEGIN
// Key structure used in site LUT mapping cache
struct SiteLutMappingKey {
+ // Maximum number of LUT cells
+ static constexpr size_t MAX_LUT_CELLS = 8;
+ // Maximum number of LUT inputs per cell
+ static constexpr size_t MAX_LUT_INPUTS = 6;
+
// LUT Cell data
struct Cell {
IdString type; // Cell type
@@ -35,51 +40,46 @@ struct SiteLutMappingKey {
// Port to net assignments. These are local net ids generated during
// key creation. This is to abstract connections from actual design
- // net names.
- dict<IdString, int32_t> conns;
-
- bool operator == (const Cell& other) const {
- return (type == other.type) &&
- (belIndex == other.belIndex) &&
- (conns == other.conns);
- }
-
- bool operator < (const Cell& other) const {
- return belIndex < other.belIndex;
- }
+ // net names. the Id 0 means unconnected.
+ int32_t conns [MAX_LUT_INPUTS];
};
int32_t tileType; // Tile type
int32_t siteType; // Site type in that tile type
std::vector<Cell> cells; // LUT cell data
+ unsigned int hash_; // Precomputed hash
+
static SiteLutMappingKey create (const SiteInformation& siteInfo);
+
+ void computeHash () {
+ hash_ = mkhash(0, tileType);
+ hash_ = mkhash(hash_, siteType);
+ for (const auto& cell : cells) {
+ hash_ = mkhash(hash_, cell.type.index);
+ hash_ = mkhash(hash_, cell.belIndex);
+ for (size_t i=0; i<MAX_LUT_INPUTS; ++i) {
+ hash_ = mkhash(hash_, cell.conns[i]);
+ }
+ }
+ }
bool operator == (const SiteLutMappingKey &other) const {
- return (tileType == other.tileType) &&
+ return (hash_ == other.hash_) &&
+ (tileType == other.tileType) &&
(siteType == other.siteType) &&
(cells == other.cells);
}
bool operator != (const SiteLutMappingKey &other) const {
- return (tileType != other.tileType) ||
+ return (hash_ != other.hash_) ||
+ (tileType != other.tileType) ||
(siteType != other.siteType) ||
(cells != other.cells);
}
unsigned int hash () const {
- unsigned int h = 0;
- h = mkhash(h, tileType);
- h = mkhash(h, siteType);
- for (const auto& cell : cells) {
- h = mkhash(h, cell.type.index);
- h = mkhash(h, cell.belIndex);
- for (const auto& conn : cell.conns) {
- h = mkhash(h, conn.first.index);
- h = mkhash(h, conn.second);
- }
- }
- return h;
+ return hash_;
}
};