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| author | gatecat <gatecat@ds0.me> | 2021-04-09 14:33:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-09 14:33:12 +0100 |
| commit | b5731cee024b1f5a04fc42ae470750df28650be6 (patch) | |
| tree | 75ccddc2f0808c80dd2c5128e3de4f713be5060f /fpga_interchange/site_arch.impl.h | |
| parent | 9cc09207fc0a3ac4e4457e3f868f5d685f640640 (diff) | |
| parent | 93e34b8754d96d3f4ffeddad9b3baf5d5cb378b0 (diff) | |
| download | nextpnr-b5731cee024b1f5a04fc42ae470750df28650be6.tar.gz nextpnr-b5731cee024b1f5a04fc42ae470750df28650be6.tar.bz2 nextpnr-b5731cee024b1f5a04fc42ae470750df28650be6.zip | |
Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc
interchange: Disambiguate cell and bel pins when creating Vcc ties
Diffstat (limited to 'fpga_interchange/site_arch.impl.h')
0 files changed, 0 insertions, 0 deletions