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| author | gatecat <gatecat@ds0.me> | 2021-03-29 18:23:16 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-29 18:23:16 +0100 |
| commit | 692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3 (patch) | |
| tree | ebe474f5cacc1206b083c7a09e77d431b4a61e61 /fpga_interchange/site_arch.h | |
| parent | 4419c36db5556d2a7f600517d6a4b5673067579d (diff) | |
| parent | f33d02dca9f6080c2497a4e058554c9908677888 (diff) | |
| download | nextpnr-692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3.tar.gz nextpnr-692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3.tar.bz2 nextpnr-692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3.zip | |
Merge pull request #645 from litghost/add_counter_and_ram
FPGA interchange: Add counter and ram tests
Diffstat (limited to 'fpga_interchange/site_arch.h')
| -rw-r--r-- | fpga_interchange/site_arch.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/fpga_interchange/site_arch.h b/fpga_interchange/site_arch.h index 95b6fcba..91330aa0 100644 --- a/fpga_interchange/site_arch.h +++ b/fpga_interchange/site_arch.h @@ -25,6 +25,7 @@ #include <unordered_set> #include <vector> +#include "PhysicalNetlist.capnp.h" #include "arch_iterators.h" #include "chipdb.h" #include "hash_table.h" @@ -295,6 +296,11 @@ struct SiteArch // Can this site pip optional invert its signal? inline bool canInvert(const SitePip &site_pip) const NPNR_ALWAYS_INLINE; + // For a site port, returns the preferred constant net type. + // + // If no preference, then NetType is SIGNAL. + inline PhysicalNetlist::PhysNetlist::NetType prefered_constant_net_type(const SitePip &site_pip) const; + inline SitePipDownhillRange getPipsDownhill(const SiteWire &site_wire) const NPNR_ALWAYS_INLINE; inline SitePipUphillRange getPipsUphill(const SiteWire &site_wire) const NPNR_ALWAYS_INLINE; SiteWireRange getWires() const; |