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| author | gatecat <gatecat@ds0.me> | 2021-02-19 08:41:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-19 08:41:58 +0000 |
| commit | 5dcb59b13decab276ac736b0b06b4ccebcf83f62 (patch) | |
| tree | 67017806da1d36a6ec13fc538390b875b30309ab /fpga_interchange/main.cc | |
| parent | b4a97efe4da95084ba5585c48d20681f68742fd4 (diff) | |
| parent | c21e23b3eb6fee48c2b2da384b2dd0cd2d4ad91f (diff) | |
| download | nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.gz nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.bz2 nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.zip | |
Merge pull request #576 from litghost/add_cell_bel_pin_mapping
Complete FPGA interchange Arch to the point where it can route a wire
Diffstat (limited to 'fpga_interchange/main.cc')
| -rw-r--r-- | fpga_interchange/main.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/fpga_interchange/main.cc b/fpga_interchange/main.cc index 48b07584..5a49cbdc 100644 --- a/fpga_interchange/main.cc +++ b/fpga_interchange/main.cc @@ -20,7 +20,9 @@ #ifdef MAIN_EXECUTABLE +#include <chrono> #include <fstream> + #include "command.h" #include "design_utils.h" #include "jsonwrite.h" @@ -67,6 +69,7 @@ void FpgaInterchangeCommandHandler::customBitstream(Context *ctx) std::unique_ptr<Context> FpgaInterchangeCommandHandler::createContext(std::unordered_map<std::string, Property> &values) { + auto start = std::chrono::high_resolution_clock::now(); ArchArgs chipArgs; if (!vm.count("chipdb")) { log_error("chip database binary must be provided\n"); @@ -88,6 +91,9 @@ std::unique_ptr<Context> FpgaInterchangeCommandHandler::createContext(std::unord } } + auto end = std::chrono::high_resolution_clock::now(); + log_info("createContext time %.02fs\n", std::chrono::duration<float>(end - start).count()); + return ctx; } |