diff options
author | gatecat <gatecat@ds0.me> | 2021-06-02 10:01:36 +0100 |
---|---|---|
committer | gatecat <gatecat@ds0.me> | 2021-06-02 15:05:19 +0100 |
commit | ecc19c2c083f7e3ed7da95557731ded803d2cb1d (patch) | |
tree | 864780d38cb9a49b6846a0045ac93e1b4dfcc88d /fpga_interchange/luts.h | |
parent | f4fed62c05a9595e22a8ec54add5531225911741 (diff) | |
download | nextpnr-ecc19c2c083f7e3ed7da95557731ded803d2cb1d.tar.gz nextpnr-ecc19c2c083f7e3ed7da95557731ded803d2cb1d.tar.bz2 nextpnr-ecc19c2c083f7e3ed7da95557731ded803d2cb1d.zip |
Using hashlib in arches
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/luts.h')
-rw-r--r-- | fpga_interchange/luts.h | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/fpga_interchange/luts.h b/fpga_interchange/luts.h index df0ac124..cbb817c9 100644 --- a/fpga_interchange/luts.h +++ b/fpga_interchange/luts.h @@ -20,14 +20,11 @@ #ifndef LUTS_H #define LUTS_H -#include <unordered_map> -#include <unordered_set> - #include "idstring.h" #include "nextpnr_namespaces.h" #include "dynamic_bitarray.h" -#include "hash_table.h" +#include "hashlib.h" NEXTPNR_NAMESPACE_BEGIN @@ -45,8 +42,8 @@ struct LutCell { // LUT cell pins for equation, LSB first. std::vector<IdString> pins; - std::unordered_set<IdString> lut_pins; - std::unordered_set<IdString> vcc_pins; + pool<IdString> lut_pins; + pool<IdString> vcc_pins; DynamicBitarray<> equation; }; @@ -56,7 +53,7 @@ struct LutBel // LUT BEL pins to LUT array index. std::vector<IdString> pins; - std::unordered_map<IdString, size_t> pin_to_index; + dict<IdString, size_t> pin_to_index; IdString output_pin; @@ -71,18 +68,18 @@ struct LutBel // Work forward from cell definition and cell -> bel pin map and check that // equation is valid. -void check_equation(const LutCell &lut_cell, const std::unordered_map<IdString, IdString> &cell_to_bel_map, - const LutBel &lut_bel, const std::vector<LogicLevel> &equation, uint32_t used_pins); +void check_equation(const LutCell &lut_cell, const dict<IdString, IdString> &cell_to_bel_map, const LutBel &lut_bel, + const std::vector<LogicLevel> &equation, uint32_t used_pins); struct LutElement { size_t width; - std::unordered_map<IdString, LutBel> lut_bels; + dict<IdString, LutBel> lut_bels; void compute_pin_order(); std::vector<IdString> pins; - std::unordered_map<IdString, size_t> pin_to_index; + dict<IdString, size_t> pin_to_index; }; struct LutMapper @@ -92,7 +89,7 @@ struct LutMapper std::vector<CellInfo *> cells; - bool remap_luts(const Context *ctx, HashTables::HashSet<const LutBel *> *blocked_luts); + bool remap_luts(const Context *ctx, pool<const LutBel *, hash_ptr_ops> *blocked_luts); // Determine which wires given the current mapping must be tied to the // default constant. @@ -101,7 +98,7 @@ struct LutMapper // the pin is free to be a signal. uint32_t check_wires(const std::vector<std::vector<int32_t>> &bel_to_cell_pin_remaps, const std::vector<const LutBel *> &lut_bels, uint32_t used_pins, - HashTables::HashSet<const LutBel *> *blocked_luts) const; + pool<const LutBel *, hash_ptr_ops> *blocked_luts) const; // Version of check_wires that uses current state of cells based on pin // mapping in cells variable. |