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| author | gatecat <gatecat@ds0.me> | 2021-06-10 13:10:29 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-06-10 13:10:29 +0100 |
| commit | e9d5b75d1d9333d359e576508235c7e35002b1c8 (patch) | |
| tree | c5c5ac59588312f8ff18294eee7a30c163b3f269 /fpga_interchange/examples | |
| parent | 13c037cc0847d8eea94dabf719ca17dad69254c9 (diff) | |
| download | nextpnr-e9d5b75d1d9333d359e576508235c7e35002b1c8.tar.gz nextpnr-e9d5b75d1d9333d359e576508235c7e35002b1c8.tar.bz2 nextpnr-e9d5b75d1d9333d359e576508235c7e35002b1c8.zip | |
ecp5: Add missing clock edge assignments
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/examples')
0 files changed, 0 insertions, 0 deletions