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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-18 16:51:05 -0800 |
|---|---|---|
| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-23 14:09:27 -0800 |
| commit | cf554f9338db84fa0d12afd83e10f7791e62efa1 (patch) | |
| tree | 54fb24ca161d1717462240d9cbc54188f6b474c5 /fpga_interchange/examples | |
| parent | 3e5a23ed5b25570c33669dfd8bdd226016968bb5 (diff) | |
| download | nextpnr-cf554f9338db84fa0d12afd83e10f7791e62efa1.tar.gz nextpnr-cf554f9338db84fa0d12afd83e10f7791e62efa1.tar.bz2 nextpnr-cf554f9338db84fa0d12afd83e10f7791e62efa1.zip | |
Add constant network test case.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/examples')
| -rw-r--r-- | fpga_interchange/examples/const_wire/Makefile | 8 | ||||
| -rw-r--r-- | fpga_interchange/examples/const_wire/run.tcl | 14 | ||||
| -rw-r--r-- | fpga_interchange/examples/const_wire/wire.v | 6 | ||||
| -rw-r--r-- | fpga_interchange/examples/const_wire/wire.xdc | 5 | ||||
| -rw-r--r-- | fpga_interchange/examples/template.mk | 9 |
5 files changed, 42 insertions, 0 deletions
diff --git a/fpga_interchange/examples/const_wire/Makefile b/fpga_interchange/examples/const_wire/Makefile new file mode 100644 index 00000000..49194f53 --- /dev/null +++ b/fpga_interchange/examples/const_wire/Makefile @@ -0,0 +1,8 @@ +DESIGN := wire +DESIGN_TOP := top +PACKAGE := csg324 + +include ../template.mk + +build/wire.json: wire.v | build + yosys -c run.tcl diff --git a/fpga_interchange/examples/const_wire/run.tcl b/fpga_interchange/examples/const_wire/run.tcl new file mode 100644 index 00000000..9127be20 --- /dev/null +++ b/fpga_interchange/examples/const_wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog wire.v + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json build/wire.json diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v new file mode 100644 index 00000000..7905c92e --- /dev/null +++ b/fpga_interchange/examples/const_wire/wire.v @@ -0,0 +1,6 @@ +module top(output o, output o2); + +assign o = 1'b0; +assign o2 = 1'b1; + +endmodule diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc new file mode 100644 index 00000000..beab748e --- /dev/null +++ b/fpga_interchange/examples/const_wire/wire.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N15 [get_ports o] +set_property PACKAGE_PIN N16 [get_ports o2] + +set_property IOSTANDARD LVCMOS33 [get_ports o] +set_property IOSTANDARD LVCMOS33 [get_ports o2] diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk index 819cdb1f..d12a4e11 100644 --- a/fpga_interchange/examples/template.mk +++ b/fpga_interchange/examples/template.mk @@ -46,6 +46,15 @@ build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys phys_yaml: build/$(DESIGN)_phys.yaml +verbose: build/$(DESIGN).netlist + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --xdc $(DESIGN).xdc \ + --netlist build/$(DESIGN).netlist \ + --phys build/$(DESIGN).phys \ + --package $(PACKAGE) \ + --verbose + debug: build/$(DESIGN).netlist gdb --args $(NEXTPNR_BIN) \ --chipdb $(BBA_PATH) \ |