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author | gatecat <gatecat@ds0.me> | 2021-03-17 14:05:49 +0000 |
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committer | GitHub <noreply@github.com> | 2021-03-17 14:05:49 +0000 |
commit | 5feea4497f416eafdf54f34c2b9c67ddcef3f26f (patch) | |
tree | e92427a879159b38441e6b3fc4f0e45ebc75e579 /fpga_interchange/examples/tests/counter | |
parent | 701587241fb8d4b490c4998ab3f2590bc09d7f55 (diff) | |
parent | 01a95faf211d5947415ed6a9ea2b1fbedf1074cd (diff) | |
download | nextpnr-5feea4497f416eafdf54f34c2b9c67ddcef3f26f.tar.gz nextpnr-5feea4497f416eafdf54f34c2b9c67ddcef3f26f.tar.bz2 nextpnr-5feea4497f416eafdf54f34c2b9c67ddcef3f26f.zip |
Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchange
Add CMake infrastructure for fpga interchange
Diffstat (limited to 'fpga_interchange/examples/tests/counter')
6 files changed, 90 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt new file mode 100644 index 00000000..dc41d8da --- /dev/null +++ b/fpga_interchange/examples/tests/counter/CMakeLists.txt @@ -0,0 +1,21 @@ +add_interchange_test( + name counter_basys3 + family ${family} + device xc7a35t + package cpg236 + tcl run.tcl + xdc counter_basys3.xdc + sources counter.v + techmap remap.v +) + +add_interchange_test( + name counter_arty + family ${family} + device xc7a35t + package csg324 + tcl run.tcl + xdc counter_arty.xdc + sources counter.v + techmap remap.v +) diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v new file mode 100644 index 00000000..00f52a20 --- /dev/null +++ b/fpga_interchange/examples/tests/counter/counter.v @@ -0,0 +1,15 @@ +module top(input clk, input rst, output [7:4] io_led); + +reg [31:0] counter = 32'b0; + +assign io_led = counter >> 22; + +always @(posedge clk) +begin + if(rst) + counter <= 32'b0; + else + counter <= counter + 1; +end + +endmodule diff --git a/fpga_interchange/examples/tests/counter/counter_arty.xdc b/fpga_interchange/examples/tests/counter/counter_arty.xdc new file mode 100644 index 00000000..c6873df5 --- /dev/null +++ b/fpga_interchange/examples/tests/counter/counter_arty.xdc @@ -0,0 +1,14 @@ +## basys3 breakout board +set_property PACKAGE_PIN E3 [get_ports clk] +set_property PACKAGE_PIN C2 [get_ports rst] +set_property PACKAGE_PIN N15 [get_ports io_led[4]] +set_property PACKAGE_PIN N16 [get_ports io_led[5]] +set_property PACKAGE_PIN P17 [get_ports io_led[6]] +set_property PACKAGE_PIN R17 [get_ports io_led[7]] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports rst] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]] diff --git a/fpga_interchange/examples/tests/counter/counter_basys3.xdc b/fpga_interchange/examples/tests/counter/counter_basys3.xdc new file mode 100644 index 00000000..09446b5f --- /dev/null +++ b/fpga_interchange/examples/tests/counter/counter_basys3.xdc @@ -0,0 +1,14 @@ +## basys3 breakout board +set_property PACKAGE_PIN W5 [get_ports clk] +set_property PACKAGE_PIN V17 [get_ports rst] +set_property PACKAGE_PIN U16 [get_ports io_led[4]] +set_property PACKAGE_PIN E19 [get_ports io_led[5]] +set_property PACKAGE_PIN U19 [get_ports io_led[6]] +set_property PACKAGE_PIN V19 [get_ports io_led[7]] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports rst] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]] diff --git a/fpga_interchange/examples/tests/counter/remap.v b/fpga_interchange/examples/tests/counter/remap.v new file mode 100644 index 00000000..6dfc0b4a --- /dev/null +++ b/fpga_interchange/examples/tests/counter/remap.v @@ -0,0 +1,11 @@ +module INV(input I, output O); + +LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O)); + +endmodule + +module BUF(input I, output O); + +LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O)); + +endmodule diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl new file mode 100644 index 00000000..ffea3b2e --- /dev/null +++ b/fpga_interchange/examples/tests/counter/run.tcl @@ -0,0 +1,15 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp +techmap -map $::env(TECHMAP) + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) |