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author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-16 12:24:15 -0800 |
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committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-17 12:03:16 -0800 |
commit | 5a7f83c705d6ea52e9e5bb7b182b32040d15a13a (patch) | |
tree | 7e9d54dca77f867e76d034923dba95e1f52980ef /fpga_interchange/examples/template.mk | |
parent | 7c1544f4d8e5dc75d6d6a8cf973888f5c94bd1b9 (diff) | |
download | nextpnr-5a7f83c705d6ea52e9e5bb7b182b32040d15a13a.tar.gz nextpnr-5a7f83c705d6ea52e9e5bb7b182b32040d15a13a.tar.bz2 nextpnr-5a7f83c705d6ea52e9e5bb7b182b32040d15a13a.zip |
Add examples invoking FPGA interchange nextpnr.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/examples/template.mk')
-rw-r--r-- | fpga_interchange/examples/template.mk | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk new file mode 100644 index 00000000..11710058 --- /dev/null +++ b/fpga_interchange/examples/template.mk @@ -0,0 +1,68 @@ +NEXTPNR_PATH := $(shell echo ~/cat_x/nextpnr) +NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange +BBA_PATH := $(NEXTPNR_PATH)/build/test.bin + +RAPIDWRIGHT_PATH := $(shell echo ~/cat_x/RapidWright) + +INTERCHANGE_PATH := $(NEXTPNR_PATH)/3rdparty/fpga-interchange-schema/interchange + +DEVICE := $(shell echo ~/cat_x/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device) + +.DELETE_ON_ERROR: +.PHONY: all debug clean + +all: build/$(DESIGN).dcp + +build: + mkdir build + +build/$(DESIGN).netlist: build/$(DESIGN).json + /usr/bin/time -v python3 -mfpga_interchange.yosys_json \ + --schema_dir $(INTERCHANGE_PATH) \ + --device $(DEVICE) \ + --top $(DESIGN_TOP) \ + build/$(DESIGN).json \ + build/$(DESIGN).netlist + +build/$(DESIGN)_netlist.yaml: build/$(DESIGN).netlist + /usr/bin/time -v python3 -mfpga_interchange.convert \ + --schema_dir $(INTERCHANGE_PATH) \ + --schema logical \ + --input_format capnp \ + --output_format yaml \ + build/$(DESIGN).netlist \ + build/$(DESIGN)_netlist.yaml + +build/$(DESIGN).phys: build/$(DESIGN).netlist + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --xdc $(DESIGN).xdc \ + --netlist build/$(DESIGN).netlist \ + --phys build/$(DESIGN).phys \ + --package $(PACKAGE) + +build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys + /usr/bin/time -v python3 -mfpga_interchange.convert \ + --schema_dir $(INTERCHANGE_PATH) \ + --schema physical \ + --input_format capnp \ + --output_format yaml \ + build/$(DESIGN).phys \ + build/$(DESIGN)_phys.yaml + +debug: build/$(DESIGN).netlist + gdb --args $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --xdc $(DESIGN).xdc \ + --netlist build/$(DESIGN).netlist \ + --phys build/$(DESIGN).phys \ + --package $(PACKAGE) + +build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc + RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \ + $(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \ + com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \ + build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp + +clean:: + rm -rf build |