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| author | gatecat <gatecat@ds0.me> | 2021-12-30 09:08:02 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-12-30 11:54:08 +0000 |
| commit | 59874188a6800fbaa03ec21e3578160e963c2eb5 (patch) | |
| tree | 28463b159ce424cdf7780174f1fffb421d04bf88 /fpga_interchange/examples/remap_xilinx.v | |
| parent | c272d28e575bde2675a6ae7090a0d5f0f4c9c88f (diff) | |
| download | nextpnr-59874188a6800fbaa03ec21e3578160e963c2eb5.tar.gz nextpnr-59874188a6800fbaa03ec21e3578160e963c2eb5.tar.bz2 nextpnr-59874188a6800fbaa03ec21e3578160e963c2eb5.zip | |
generic: Refactor for faster performance
This won't affect Python-built arches significantly; but will be useful
for the future 'viaduct' functionality where generic routing graphs can
be built on the C++ side; too.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/examples/remap_xilinx.v')
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