Add initial logic for handling dedicated interconnect situations.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v
new file mode 100644
index 00000000..1c271042
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.v
@@ -0,0 +1,11 @@
+module top(input clk, input d, input r, output reg q);
+
+always @(posedge clk)
+begin
+    if(r)
+        q <= 1'b0;
+    else
+        q <= d;
+end
+
+endmodule