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| author | gatecat <gatecat@ds0.me> | 2021-02-25 10:22:45 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-25 10:22:45 +0000 |
| commit | ab8dfcfba4544c6733d074b24b0529d431b66d29 (patch) | |
| tree | af212992fee7cd0a8fb27d19d0137587402fdc1b /fpga_interchange/examples/archcheck | |
| parent | e2cdaa653c805f9bfb6f0ab36295858e5dd3179d (diff) | |
| parent | a30043c8da1b1cc46a2dcfb90aa3a06d4f4ed4e9 (diff) | |
| download | nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.tar.gz nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.tar.bz2 nextpnr-ab8dfcfba4544c6733d074b24b0529d431b66d29.zip | |
Merge pull request #591 from litghost/add_constant_network
Add constant network support to FPGA interchange arch
Diffstat (limited to 'fpga_interchange/examples/archcheck')
| -rw-r--r-- | fpga_interchange/examples/archcheck/Makefile | 7 | ||||
| -rw-r--r-- | fpga_interchange/examples/archcheck/test_data.yaml | 29 |
2 files changed, 36 insertions, 0 deletions
diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile index cf82013b..02e1c08e 100644 --- a/fpga_interchange/examples/archcheck/Makefile +++ b/fpga_interchange/examples/archcheck/Makefile @@ -13,4 +13,11 @@ check: check_test_data check_test_data: $(NEXTPNR_BIN) \ --chipdb $(BBA_PATH) \ + --package $(PACKAGE) \ + --run $(NEXTPNR_PATH)/python/check_arch_api.py + +debug_check_test_data: + gdb --args $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --package $(PACKAGE) \ --run $(NEXTPNR_PATH)/python/check_arch_api.py diff --git a/fpga_interchange/examples/archcheck/test_data.yaml b/fpga_interchange/examples/archcheck/test_data.yaml index b41112cf..268d180a 100644 --- a/fpga_interchange/examples/archcheck/test_data.yaml +++ b/fpga_interchange/examples/archcheck/test_data.yaml @@ -1,7 +1,36 @@ pip_test: - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 dst_wire: SLICE_X15Y93.SLICEL/D3 +pip_chain_test: + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE + - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0 + - INT_R_X3Y145/GND_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE + - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1 + - INT_R_X3Y145/VCC_WIRE + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - $CONSTANTS_X0Y0/$VCC_NODE + - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE + - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1 + - wires: + - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - $CONSTANTS_X0Y0/$GND_NODE + - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE + - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0 bel_pin_test: - bel: SLICE_X15Y93.SLICEL/D6LUT pin: A3 wire: SLICE_X15Y93.SLICEL/D3 + - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND + pin: G + wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE + - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC + pin: P + wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE |