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| author | Maciej Dudek <mdudek@antmicro.com> | 2021-08-30 11:12:49 +0200 |
|---|---|---|
| committer | Maciej Dudek <mdudek@antmicro.com> | 2021-09-23 15:43:23 +0200 |
| commit | fdcfe8cd8188b6c4ea2450843bd22d822856a091 (patch) | |
| tree | d23b1e69f725e9cd3cda0f45162014b75eb36840 /fpga_interchange/chipdb.h | |
| parent | d9a71083e1a081f89e1aa4c357bc3b828eea6709 (diff) | |
| download | nextpnr-fdcfe8cd8188b6c4ea2450843bd22d822856a091.tar.gz nextpnr-fdcfe8cd8188b6c4ea2450843bd22d822856a091.tar.bz2 nextpnr-fdcfe8cd8188b6c4ea2450843bd22d822856a091.zip | |
Adding support for MacroCells
Diffstat (limited to 'fpga_interchange/chipdb.h')
| -rw-r--r-- | fpga_interchange/chipdb.h | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index 85dc7f25..1086976a 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -34,7 +34,12 @@ NEXTPNR_NAMESPACE_BEGIN * kExpectedChipInfoVersion */ -static constexpr int32_t kExpectedChipInfoVersion = 14; +static constexpr int32_t kExpectedChipInfoVersion = 15; + +NPNR_PACKED_STRUCT(struct BelConnectedPinsPOD { + uint32_t pin1; + uint32_t pin2; +}); // Flattened site indexing. // @@ -80,6 +85,8 @@ NPNR_PACKED_STRUCT(struct BelInfoPOD { int8_t inverting_pin; int16_t padding; + + RelSlice<BelConnectedPinsPOD> connected_pins; }); enum BELCategory @@ -416,13 +423,45 @@ NPNR_PACKED_STRUCT(struct ChainablePortPOD { int16_t avg_y_offset; }); +NPNR_PACKED_STRUCT(struct ClusterRequiredCellPOD{ + uint32_t name; + uint32_t count; +}); + +NPNR_PACKED_STRUCT(struct ClusterUsedPortPOD{ + uint32_t name; +}); + +NPNR_PACKED_STRUCT(struct ClusterEdgePOD{ + uint32_t dir; + uint32_t cell_pin; + uint32_t other_cell_pin; + uint32_t other_cell_type; +}); + +NPNR_PACKED_STRUCT(struct ClusterConnectionsPOD{ + uint32_t target_idx; + RelSlice<ClusterEdgePOD> edges; +}); + +NPNR_PACKED_STRUCT(struct ClusterConnectionGraphPOD{ + uint32_t idx; + uint32_t cell_type; + RelSlice<ClusterConnectionsPOD> connections; + RelSlice<ClusterUsedPortPOD> used_ports; +}); + + NPNR_PACKED_STRUCT(struct ClusterPOD { uint32_t name; RelSlice<uint32_t> root_cell_types; RelSlice<ChainablePortPOD> chainable_ports; RelSlice<ClusterCellPortPOD> cluster_cells_map; + RelSlice<ClusterRequiredCellPOD> required_cells; + RelSlice<ClusterConnectionGraphPOD> connection_graph; uint32_t out_of_site_clusters; uint32_t disallow_other_cells; + uint32_t from_macro; }); NPNR_PACKED_STRUCT(struct ChipInfoPOD { |