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| author | Alessandro Comodi <acomodi@antmicro.com> | 2021-07-07 19:16:48 +0200 |
|---|---|---|
| committer | Alessandro Comodi <acomodi@antmicro.com> | 2021-07-08 16:51:23 +0200 |
| commit | dc0819b01a6bb976ea29151da2cd95e8227f8e08 (patch) | |
| tree | 0a22dd1c2415ad27b809f1101c07306752bf1ea0 /fpga_interchange/chipdb.h | |
| parent | 6829e4c197758a4bd68449e4843a6b3992ca3723 (diff) | |
| download | nextpnr-dc0819b01a6bb976ea29151da2cd95e8227f8e08.tar.gz nextpnr-dc0819b01a6bb976ea29151da2cd95e8227f8e08.tar.bz2 nextpnr-dc0819b01a6bb976ea29151da2cd95e8227f8e08.zip | |
interchange: reduce run-time to check dedicated interconnect
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/chipdb.h')
| -rw-r--r-- | fpga_interchange/chipdb.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h index fde35e7f..6879f02a 100644 --- a/fpga_interchange/chipdb.h +++ b/fpga_interchange/chipdb.h @@ -421,6 +421,7 @@ NPNR_PACKED_STRUCT(struct ClusterPOD { RelSlice<uint32_t> root_cell_types; RelSlice<ChainablePortPOD> chainable_ports; RelSlice<ClusterCellPortPOD> cluster_cells_map; + uint32_t out_of_site_clusters; }); NPNR_PACKED_STRUCT(struct ChipInfoPOD { |