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| author | gatecat <gatecat@ds0.me> | 2021-05-09 18:28:49 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-15 14:54:33 +0100 |
| commit | ad5e5f80ca4ad798d1afbddcae84e04f3a26f0e5 (patch) | |
| tree | 7b4427c020dc2f5b58ee393d9b6eb512496a572c /fpga_interchange/cell_parameters.cc | |
| parent | a5815265288aa373c52ca1786f2303fb6eb83162 (diff) | |
| download | nextpnr-ad5e5f80ca4ad798d1afbddcae84e04f3a26f0e5.tar.gz nextpnr-ad5e5f80ca4ad798d1afbddcae84e04f3a26f0e5.tar.bz2 nextpnr-ad5e5f80ca4ad798d1afbddcae84e04f3a26f0e5.zip | |
mistral: Rename clock buffer primitive
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/cell_parameters.cc')
0 files changed, 0 insertions, 0 deletions