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authorKeith Rothman <537074+litghost@users.noreply.github.com>2021-02-16 14:51:25 -0800
committerKeith Rothman <537074+litghost@users.noreply.github.com>2021-02-17 12:03:16 -0800
commit7c1544f4d8e5dc75d6d6a8cf973888f5c94bd1b9 (patch)
tree842b999ee2af18571b97ce22bffa537b8856a25c /fpga_interchange/arch_pack_io.cc
parent6f1c835221d18199962273def4386e0385820c67 (diff)
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Continue fixes.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/arch_pack_io.cc')
-rw-r--r--fpga_interchange/arch_pack_io.cc26
1 files changed, 23 insertions, 3 deletions
diff --git a/fpga_interchange/arch_pack_io.cc b/fpga_interchange/arch_pack_io.cc
index 16d0d05f..2bddad8b 100644
--- a/fpga_interchange/arch_pack_io.cc
+++ b/fpga_interchange/arch_pack_io.cc
@@ -118,6 +118,7 @@ void Arch::pack_ports()
// constraints between the port cell create by nextpnr and cells that are
// immediately attached to that port cell.
for (auto port_pair : port_cells) {
+ IdString port_name = port_pair.first;
CellInfo *port_cell = port_pair.second;
std::unordered_set<CellInfo *> tightly_attached_bels;
@@ -135,6 +136,13 @@ void Arch::pack_ports()
}
}
+ if(getCtx()->verbose) {
+ log_info("Tightly attached BELs for port %s\n", port_name.c_str(getCtx()));
+ for(CellInfo * cell : tightly_attached_bels) {
+ log_info(" - %s : %s\n", cell->name.c_str(getCtx()), cell->type.c_str(getCtx()));
+ }
+ }
+
NPNR_ASSERT(tightly_attached_bels.erase(port_cell) == 1);
std::unordered_set<IdString> cell_types_in_io_group;
for (CellInfo *cell : tightly_attached_bels) {
@@ -163,6 +171,10 @@ void Arch::pack_ports()
}
}
+ if(possible_site_types.empty()) {
+ log_error("Port '%s' has no possible site types!\n", port_name.c_str(getCtx()));
+ }
+
auto iter = port_cell->attrs.find(id("PACKAGE_PIN"));
if (iter == port_cell->attrs.end()) {
// FIXME: Relax this constraint
@@ -176,11 +188,12 @@ void Arch::pack_ports()
log_error("Package pin '%s' not found in part %s\n", package_pin_id.c_str(getCtx()), get_part().c_str());
}
NPNR_ASSERT(pin_iter != package_pin_bels.end());
+ const auto &site_type_to_bel = pin_iter->second;
BelId package_bel;
for (IdString site_type : possible_site_types) {
- auto site_iter = pin_iter->second.find(site_type);
- if (site_iter != pin_iter->second.end()) {
+ auto site_iter = site_type_to_bel.find(site_type);
+ if (site_iter != site_type_to_bel.end()) {
// FIXME: Need to handle case where a port can be in multiple
// modes, but only one of the modes works.
//
@@ -188,7 +201,14 @@ void Arch::pack_ports()
package_bel = site_iter->second;
}
}
- NPNR_ASSERT(package_bel != BelId());
+
+ if(package_bel == BelId()) {
+ log_info("Failed to find BEL for package pin '%s' in any possible site types:\n", package_pin_id.c_str(getCtx()));
+ for (IdString site_type : possible_site_types) {
+ log_info(" - %s\n", site_type.c_str(getCtx()));
+ }
+ log_error("Failed to find BEL for package pin '%s'\n", package_pin_id.c_str(getCtx()));
+ }
std::unordered_set<CellInfo *> placed_cells;
bindBel(package_bel, port_cell, STRENGTH_FIXED);