Start adding visible wires

5 files changed, 99 insertions, 10 deletions

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 9344ff5e..709f1c3f 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -620,7 +620,26 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
             ret.push_back(el);
         }
     }
+    if (decal.type == DecalId::TYPE_WIRE) {
+        WireId wire;
+        wire.index = decal.z;
+        wire.location = decal.location;
+        auto wire_type = getWireType(wire);
+        int x = decal.location.x;
+        int y = chip_info->height - 1 - decal.location.y;
 
+        GfxTileWireId tilewire = GfxTileWireId(locInfo(wire)->wire_data[wire.index].tile_wire);
+        if (wire_type == id_WIRE_TYPE_SLICE && tilewire != GfxTileWireId::TILE_WIRE_NONE) {
+            GraphicElement el;
+            el.type = GraphicElement::TYPE_LINE;
+            el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
+            el.x1 = x + slice_x1 - 0.005f;
+            el.x2 = x + slice_x1;
+            el.y1 = y + slice_y2 - 0.0017f * tilewire;
+            el.y2 = y + slice_y2 - 0.0017f * tilewire;
+            ret.push_back(el);
+        }        
+    }
     if (decal.type == DecalId::TYPE_BEL) {
         BelId bel;
         bel.index = decal.z;
@@ -674,7 +693,15 @@ DecalXY Arch::getBelDecal(BelId bel) const
     return decalxy;
 }
 
-DecalXY Arch::getWireDecal(WireId wire) const { return {}; }
+DecalXY Arch::getWireDecal(WireId wire) const
+{
+    DecalXY decalxy;
+    decalxy.decal.type = DecalId::TYPE_WIRE;
+    decalxy.decal.location = wire.location;
+    decalxy.decal.z = wire.index;
+    decalxy.decal.active = false;
+    return decalxy;    
+}
 
 DecalXY Arch::getPipDecal(PipId pip) const { return {}; };
 
@@ -1171,4 +1198,14 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 // -----------------------------------------------------------------------
 
+
+std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
+{
+    std::vector<std::pair<IdString, std::string>> ret;
+    auto &wi = locInfo(wire)->wire_data[wire.index];
+
+    ret.push_back(std::make_pair(id("TILE_WIRE_ID"), stringf("%d", wi.tile_wire)));
+
+    return ret;
+}
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch.h b/ecp5/arch.h
index f6ba1a7b..815dae0c 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -85,6 +85,7 @@ NPNR_PACKED_STRUCT(struct PipLocatorPOD {
 NPNR_PACKED_STRUCT(struct WireInfoPOD {
     RelPtr<char> name;
     int32_t type;
+    int32_t tile_wire;
     int32_t num_uphill, num_downhill;
     RelPtr<PipLocatorPOD> pips_uphill, pips_downhill;
 
@@ -648,11 +649,7 @@ struct Arch : BaseCtx
         return id;
     }
 
-    std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const
-    {
-        std::vector<std::pair<IdString, std::string>> ret;
-        return ret;
-    }
+    std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const;
 
     uint32_t getWireChecksum(WireId wire) const { return wire.index; }
 
diff --git a/ecp5/family.cmake b/ecp5/family.cmake
index 5512e7dd..b0b520d7 100644
--- a/ecp5/family.cmake
+++ b/ecp5/family.cmake
@@ -41,14 +41,15 @@ if (NOT EXTERNAL_CHIPDB)
             set(DEV_CC_DB ${CMAKE_CURRENT_BINARY_DIR}/ecp5/chipdbs/chipdb-${dev}.bin)
             set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba)
             set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/constids.inc)
+            set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/gfx.h)
             if (PREGENERATED_BBA_PATH)
                 add_custom_command(OUTPUT ${DEV_CC_DB}
                     COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${PREGENERATED_BBA_PATH}/chipdb-${dev}.bba ${DEV_CC_DB}
                     )
             else()
                 add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
-                    COMMAND ${ENV_CMD} ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} ${dev} > ${DEV_CC_BBA_DB}
-                    DEPENDS ${DB_PY} ${PREV_DEV_CC_BBA_DB}
+                    COMMAND ${ENV_CMD} ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${dev} > ${DEV_CC_BBA_DB}
+                    DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DB_PY} ${PREV_DEV_CC_BBA_DB}
                     )
                 add_custom_command(OUTPUT ${DEV_CC_DB}
                     COMMAND bbasm ${BBASM_ENDIAN_FLAG} ${DEV_CC_BBA_DB} ${DEV_CC_DB}
@@ -71,6 +72,7 @@ if (NOT EXTERNAL_CHIPDB)
             set(DEV_CC_DB ${CMAKE_CURRENT_BINARY_DIR}/ecp5/chipdbs/chipdb-${dev}.cc)
             set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bba)
             set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/constids.inc)
+            set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/gfx.h)
             if (PREGENERATED_BBA_PATH)
                 add_custom_command(OUTPUT ${DEV_CC_DB}
                     COMMAND bbasm --c ${BBASM_ENDIAN_FLAG} ${PREGENERATED_BBA_PATH}/chipdb-${dev}.bba ${DEV_CC_DB}.new
@@ -78,9 +80,9 @@ if (NOT EXTERNAL_CHIPDB)
                     )
             else()
                 add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
-                    COMMAND ${ENV_CMD} ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} ${dev} > ${DEV_CC_BBA_DB}.new
+                    COMMAND ${ENV_CMD} ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${dev} > ${DEV_CC_BBA_DB}.new
                     COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB}
-                    DEPENDS ${DB_PY} ${PREV_DEV_CC_BBA_DB}
+                    DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DB_PY} ${PREV_DEV_CC_BBA_DB}
                     )
                 add_custom_command(OUTPUT ${DEV_CC_DB}
                     COMMAND bbasm --c ${BBASM_ENDIAN_FLAG} ${DEV_CC_BBA_DB} ${DEV_CC_DB}.new
diff --git a/ecp5/gfx.h b/ecp5/gfx.h
index ec867547..c8d77766 100644
--- a/ecp5/gfx.h
+++ b/ecp5/gfx.h
@@ -47,6 +47,31 @@ const float io_cell_h_y1 = 0.05;
 const float io_cell_h_y2 = 0.24;
 const float io_cell_h_pitch = 0.125;
 
+enum GfxTileWireId
+{
+    TILE_WIRE_NONE,
+    
+    TILE_WIRE_D1_SLICE,
+    TILE_WIRE_C1_SLICE,
+    TILE_WIRE_B1_SLICE,
+    TILE_WIRE_A1_SLICE,
+    TILE_WIRE_D0_SLICE,
+    TILE_WIRE_C0_SLICE,
+    TILE_WIRE_B0_SLICE,
+    TILE_WIRE_A0_SLICE,
+    TILE_WIRE_DI1_SLICE,
+    TILE_WIRE_DI0_SLICE,
+    TILE_WIRE_M1_SLICE,
+    TILE_WIRE_M0_SLICE,
+    TILE_WIRE_FXBA_SLICE,
+    TILE_WIRE_FXAA_SLICE,
+    TILE_WIRE_WRE0_SLICE,
+    TILE_WIRE_WCK0_SLICE,
+    TILE_WIRE_CE0_SLICE,
+    TILE_WIRE_LSR0_SLICE,
+    TILE_WIRE_CLK0_SLICE
+};
+
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 188c6909..2ff0d0e7 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -10,12 +10,36 @@ from os import path
 location_types = dict()
 type_at_location = dict()
 tiletype_names = dict()
+gfx_wire_ids = dict()
+gfx_wire_names = list()
 
 parser = argparse.ArgumentParser(description="import ECP5 routing and bels from Project Trellis")
 parser.add_argument("device", type=str, help="target device")
 parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
+parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
 args = parser.parse_args()
 
+with open(args.gfxh) as f:
+    state = 0
+    for line in f:
+        if state == 0 and line.startswith("enum GfxTileWireId"):
+            state = 1
+        elif state == 1 and line.startswith("};"):
+            state = 0
+        elif state == 1 and (line.startswith("{") or line.strip() == ""):
+            pass
+        elif state == 1:
+            idx = len(gfx_wire_ids)
+            name = line.strip().rstrip(",")
+            gfx_wire_ids[name] = idx
+            gfx_wire_names.append(name)
+
+def gfx_wire_alias(old, new):
+    assert old in gfx_wire_ids
+    assert new not in gfx_wire_ids
+    gfx_wire_ids[new] = gfx_wire_ids[old]
+
+
 def wire_type(name):
     longname = name
     name = name.split('/')
@@ -358,6 +382,10 @@ def write_database(dev_name, chip, ddrg, endianness):
                 wire = loctype.wires[wire_idx]
                 bba.s(ddrg.to_str(wire.name), "name")
                 bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
+                if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
+                    bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
+                else:                    
+                    bba.u32(0, "tile_wire")
                 bba.u32(len(wire.arcsUphill), "num_uphill")
                 bba.u32(len(wire.arcsDownhill), "num_downhill")
                 bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")