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authorgatecat <gatecat@ds0.me>2021-12-19 16:41:34 +0000
committergatecat <gatecat@ds0.me>2021-12-19 17:15:15 +0000
commitddb084e9a8a0cba10536951236cde824526e8071 (patch)
treed03ba5688367cb476a06b19d04ca78d0352afce3 /ecp5
parent56d550733346000584b9490fac0953fe07124035 (diff)
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archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'ecp5')
-rw-r--r--ecp5/arch.cc21
-rw-r--r--ecp5/arch.h2
2 files changed, 9 insertions, 14 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 95a27682..2e453f2a 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -543,26 +543,21 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
return bb;
}
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
{
- const auto &driver = net_info->driver;
- if ((driver.port == id_FCO && sink.port == id_FCI) || sink.port == id_FXA || sink.port == id_FXB)
+ if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin == id_FXA || dst_pin == id_FXB)
return 0;
- auto driver_loc = getBelLocation(driver.cell->bel);
- auto sink_loc = getBelLocation(sink.cell->bel);
+ auto driver_loc = getBelLocation(src_bel);
+ auto sink_loc = getBelLocation(dst_bel);
// Encourage use of direct interconnect
if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) {
- if ((sink.port == id_A0 || sink.port == id_A1) && (driver.port == id_F1) &&
- (driver_loc.z == 2 || driver_loc.z == 3))
+ if ((dst_pin == id_A0 || dst_pin == id_A1) && (src_pin == id_F1) && (driver_loc.z == 2 || driver_loc.z == 3))
return 0;
- if ((sink.port == id_B0 || sink.port == id_B1) && (driver.port == id_F1) &&
- (driver_loc.z == 0 || driver_loc.z == 1))
+ if ((dst_pin == id_B0 || dst_pin == id_B1) && (src_pin == id_F1) && (driver_loc.z == 0 || driver_loc.z == 1))
return 0;
- if ((sink.port == id_C0 || sink.port == id_C1) && (driver.port == id_F0) &&
- (driver_loc.z == 2 || driver_loc.z == 3))
+ if ((dst_pin == id_C0 || dst_pin == id_C1) && (src_pin == id_F0) && (driver_loc.z == 2 || driver_loc.z == 3))
return 0;
- if ((sink.port == id_D0 || sink.port == id_D1) && (driver.port == id_F0) &&
- (driver_loc.z == 0 || driver_loc.z == 1))
+ if ((dst_pin == id_D0 || dst_pin == id_D1) && (src_pin == id_F0) && (driver_loc.z == 0 || driver_loc.z == 1))
return 0;
}
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 51a919bb..c1bed2b3 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -913,7 +913,7 @@ struct Arch : BaseArch<ArchRanges>
delay_t estimateDelay(WireId src, WireId dst) const override;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
- delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+ delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
delay_t getDelayEpsilon() const override { return 20; }
delay_t getRipupDelayPenalty() const override;
float getDelayNS(delay_t v) const override { return v * 0.001; }