Merge branch 'master' of ssh.github.com:YosysHQ/nextpnr

2 files changed, 22 insertions, 2 deletions

diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index bc8a6c55..1bdb4188 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -650,7 +650,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
     }
     // Find bank voltages
     std::unordered_map<int, IOVoltage> bankVcc;
-    std::unordered_map<int, bool> bankLvds, bankVref;
+    std::unordered_map<int, bool> bankLvds, bankVref, bankDiff;
 
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
@@ -675,6 +675,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
 
             if (iotype == "LVDS")
                 bankLvds[bank] = true;
+            if ((dir == "INPUT" || dir == "BIDIR") && is_differential(ioType_from_str(iotype)))
+                bankDiff[bank] = true;
             if ((dir == "INPUT" || dir == "BIDIR") && is_referenced(ioType_from_str(iotype)))
                 bankVref[bank] = true;
         }
@@ -698,6 +700,9 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                         cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
                         cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
                     }
+                    if (bankDiff[bank]) {
+                        cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+                    }
                     if (bankVref[bank]) {
                         cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
                         cc.tiles[tile.first].add_enum("BANK.VREF", "ON");
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index c630c2c3..7f9f1579 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -432,7 +432,13 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
         replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
-        trio->params[ctx->id("DIR")] = std::string("BIDIR");
+        NetInfo *i = get_net_or_empty(nxio, ctx->id("I"));
+        if (i == nullptr || i->driver.cell == nullptr)
+            trio->params[ctx->id("DIR")] = std::string("INPUT");
+        else {
+            log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
+            trio->params[ctx->id("DIR")] = std::string("BIDIR");
+        }
         replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
         replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
     } else {
@@ -446,6 +452,15 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
     if (dinet != nullptr && dinet->name == nxio->name)
         rename_net(ctx, dinet, ctx->id(dinet->name.str(ctx) + "$TRELLIS_IO_IN"));
 
+    if (ctx->nets.count(nxio->name)) {
+        int i = 0;
+        IdString new_name;
+        do {
+            new_name = ctx->id(nxio->name.str(ctx) + "$rename$" + std::to_string(i++));
+        } while (ctx->nets.count(new_name));
+        rename_net(ctx, ctx->nets.at(nxio->name).get(), new_name);
+    }
+
     // Create a new top port net for accurate IO timing analysis and simulation netlists
     if (ctx->ports.count(nxio->name)) {
         IdString tn_netname = nxio->name;