aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5/trellis_import.py
diff options
context:
space:
mode:
authorEddie Hung <eddie.hung+gitlab@gmail.com>2018-07-24 01:19:09 +0000
committerEddie Hung <eddie.hung+gitlab@gmail.com>2018-07-24 01:19:09 +0000
commit30ec1cfbd7dd02578fa2a3e33612e863f01ea959 (patch)
treee77d130f96c8061374318f036856aa73d431017d /ecp5/trellis_import.py
parenteeb93d6eda613c0946867118c1ff93f2462e417f (diff)
parent771edd1fda8692930e186a8913b7588d18fda710 (diff)
downloadnextpnr-30ec1cfbd7dd02578fa2a3e33612e863f01ea959.tar.gz
nextpnr-30ec1cfbd7dd02578fa2a3e33612e863f01ea959.tar.bz2
nextpnr-30ec1cfbd7dd02578fa2a3e33612e863f01ea959.zip
Merge branch 'redist_slack' into 'redist_slack'
Update budgets during routing See merge request SymbioticEDA/nextpnr!15
Diffstat (limited to 'ecp5/trellis_import.py')
-rwxr-xr-xecp5/trellis_import.py28
1 files changed, 12 insertions, 16 deletions
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index af5386e7..b5cd53f1 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -401,12 +401,12 @@ def write_database(dev_name, ddrg, endianness):
for up in wire.arcsUphill:
write_loc(up.rel, "rel_loc")
bba.u32(up.id, "index")
- if len(wire.belsDownhill) > 0:
- bba.l("loc%d_wire%d_downbels" % (idx, wire_idx), "BelPortPOD")
- for db in wire.belsDownhill:
- write_loc(db.bel.rel, "rel_bel_loc")
- bba.u32(db.bel.id, "bel_index")
- bba.u32(portpins[ddrg.to_str(db.pin)], "port")
+ if len(wire.belPins) > 0:
+ bba.l("loc%d_wire%d_belpins" % (idx, wire_idx), "BelPortPOD")
+ for bp in wire.belPins:
+ write_loc(bp.bel.rel, "rel_bel_loc")
+ bba.u32(bp.bel.id, "bel_index")
+ bba.u32(portpins[ddrg.to_str(bp.pin)], "port")
bba.l("loc%d_wires" % idx, "WireInfoPOD")
for wire_idx in range(len(loctype.wires)):
wire = loctype.wires[wire_idx]
@@ -415,28 +415,24 @@ def write_database(dev_name, ddrg, endianness):
bba.u32(len(wire.arcsDownhill), "num_downhill")
bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
bba.r("loc%d_wire%d_downpips" % (idx, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
- bba.u32(len(wire.belsDownhill), "num_bels_downhill")
- write_loc(wire.belUphill.bel.rel, "uphill_bel_loc")
- if wire.belUphill.pin != -1:
- bba.u32(wire.belUphill.bel.id, "uphill_bel_idx")
- bba.u32(portpins[ddrg.to_str(wire.belUphill.pin)], "uphill_bel_pin")
- else:
- bba.u32(0xFFFFFFFF, "bel_uphill.bel_index")
- bba.u32(0, "bel_uphill.port")
- bba.r("loc%d_wire%d_downbels" % (idx, wire_idx) if len(wire.belsDownhill) > 0 else None, "bels_downhill")
+ bba.u32(len(wire.belPins), "num_bel_pins")
+ bba.r("loc%d_wire%d_belpins" % (idx, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins")
+
if len(loctype.bels) > 0:
for bel_idx in range(len(loctype.bels)):
bel = loctype.bels[bel_idx]
- bba.l("loc%d_bel%d_wires" % (idx, bel_idx), "BelPortPOD")
+ bba.l("loc%d_bel%d_wires" % (idx, bel_idx), "BelWirePOD")
for pin in bel.wires:
write_loc(pin.wire.rel, "rel_wire_loc")
bba.u32(pin.wire.id, "wire_index")
bba.u32(portpins[ddrg.to_str(pin.pin)], "port")
+ bba.u32(int(pin.dir), "dir")
bba.l("loc%d_bels" % idx, "BelInfoPOD")
for bel_idx in range(len(loctype.bels)):
bel = loctype.bels[bel_idx]
bba.s(ddrg.to_str(bel.name), "name")
bba.u32(bel_types[ddrg.to_str(bel.type)], "type")
+ bba.u32(bel.z, "z")
bba.u32(len(bel.wires), "num_bel_wires")
bba.r("loc%d_bel%d_wires" % (idx, bel_idx), "bel_wires")