Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into gridapi

9 files changed, 44 insertions, 217 deletions

diff --git a/ecp5/synth/blinky.v b/ecp5/synth/blinky.v
index ac7c6ea3..9c6b187b 100644
--- a/ecp5/synth/blinky.v
+++ b/ecp5/synth/blinky.v
@@ -1,46 +1,46 @@
-module top(input clk_pin, input btn_pin, output [3:0] led_pin, output gpio0_pin);
+module top(input clk_pin, input btn_pin, output [7:0] led_pin, output gpio0_pin);
 
-	wire clk;
-	wire [7:0] led;
+    wire clk;
+    wire [7:0] led;
     wire btn;
     wire gpio0;
 
-	(* BEL="X0/Y35/PIOA" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk));
+    (* LOC="G2" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk));
 
-	(* BEL="X4/Y71/PIOA" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("INPUT")) btn_buf (.B(btn_pin), .O(btn));
+    (* LOC="R1" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("INPUT")) btn_buf (.B(btn_pin), .O(btn));
 
-	(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin[0]), .I(led[0]));
-	(* BEL="X0/Y23/PIOD" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_1 (.B(led_pin[1]), .I(led[1]));
-	(* BEL="X0/Y26/PIOA" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_2 (.B(led_pin[2]), .I(led[2]));
-    (* BEL="X0/Y26/PIOC" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(led_pin[3]), .I(led[3]));
+    (* LOC="B2" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin[0]), .I(led[0]));
+    (* LOC="C2" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_1 (.B(led_pin[1]), .I(led[1]));
+    (* LOC="C1" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_2 (.B(led_pin[2]), .I(led[2]));
+    (* LOC="D2" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(led_pin[3]), .I(led[3]));
 
-	(* BEL="X0/Y26/PIOB" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(led_pin[4]), .I(led[4]));
-	(* BEL="X0/Y32/PIOD" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(led_pin[5]), .I(led[5]));
-	(* BEL="X0/Y26/PIOD" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(led[6]));
-    (* BEL="X0/Y29/PIOD" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(led[7]));
+    (* LOC="D1" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(led_pin[4]), .I(led[4]));
+    (* LOC="E2" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(led_pin[5]), .I(led[5]));
+    (* LOC="E1" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(led[6]));
+    (* LOC="H3" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(led[7]));
 
 
-	(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
+    (* LOC="L2" *) (* IO_TYPE="LVCMOS33" *)
+    TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
 
     localparam ctr_width = 24;
     localparam ctr_max = 2**ctr_width - 1;
-	reg [ctr_width-1:0] ctr = 0;
-	reg [9:0] pwm_ctr = 0;
+    reg [ctr_width-1:0] ctr = 0;
+    reg [9:0] pwm_ctr = 0;
     reg dir = 0;
 
-	always@(posedge clk) begin
-		ctr <= btn ? ctr : (dir ? ctr - 1'b1 : ctr + 1'b1);
+    always@(posedge clk) begin
+        ctr <= btn ? ctr : (dir ? ctr - 1'b1 : ctr + 1'b1);
         if (ctr[ctr_width-1 : ctr_width-3] == 0 && dir == 1)
             dir <= 1'b0;
         else if (ctr[ctr_width-1 : ctr_width-3] == 7 && dir == 0)
@@ -54,24 +54,24 @@ module top(input clk_pin, input btn_pin, output [3:0] led_pin, output gpio0_pin)
 
     genvar i;
     generate
-    for (i = 0; i < 8; i=i+1) begin
-       always @ (posedge clk) begin
-            if (ctr[ctr_width-1 : ctr_width-3] == i)
-                brightness[i] <= bright_max;
-            else if (ctr[ctr_width-1 : ctr_width-3] == (i - 1))
-                brightness[i] <= ctr[ctr_width-4:ctr_width-13];
-             else if (ctr[ctr_width-1 : ctr_width-3] == (i + 1))
-                 brightness[i] <= bright_max - ctr[ctr_width-4:ctr_width-13];
-            else
-                brightness[i] <= 0;
-            led_reg[i] <= pwm_ctr < brightness[i];
-       end
-    end
+        for (i = 0; i < 8; i=i+1) begin
+            always @ (posedge clk) begin
+                if (ctr[ctr_width-1 : ctr_width-3] == i)
+                    brightness[i] <= bright_max;
+                else if (ctr[ctr_width-1 : ctr_width-3] == (i - 1))
+                    brightness[i] <= ctr[ctr_width-4:ctr_width-13];
+                else if (ctr[ctr_width-1 : ctr_width-3] == (i + 1))
+                    brightness[i] <= bright_max - ctr[ctr_width-4:ctr_width-13];
+                else
+                    brightness[i] <= 0;
+                led_reg[i] <= pwm_ctr < brightness[i];
+            end
+        end
     endgenerate
 
     assign led = led_reg;
 
     // Tie GPIO0, keep board from rebooting
-    TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
+    assign gpio0 = 1'b1;
 
 endmodule
diff --git a/ecp5/synth/blinky.ys b/ecp5/synth/blinky.ys
index c0b74636..fb359380 100644
--- a/ecp5/synth/blinky.ys
+++ b/ecp5/synth/blinky.ys
@@ -1,9 +1,2 @@
 read_verilog blinky.v
-read_verilog -lib cells.v
-synth -top top
-abc -lut 4
-techmap -map simple_map.v
-splitnets
-opt_clean
-stat
-write_json blinky.json
+synth_ecp5 -noccu2 -nomux -nodram -json blinky.json
diff --git a/ecp5/synth/blinky_nopack.ys b/ecp5/synth/blinky_nopack.ys
deleted file mode 100644
index fb359380..00000000
--- a/ecp5/synth/blinky_nopack.ys
+++ /dev/null
@@ -1,2 +0,0 @@
-read_verilog blinky.v
-synth_ecp5 -noccu2 -nomux -nodram -json blinky.json
diff --git a/ecp5/synth/cells.v b/ecp5/synth/cells.v
deleted file mode 100644
index 353b8ada..00000000
--- a/ecp5/synth/cells.v
+++ /dev/null
@@ -1,49 +0,0 @@
-(* blackbox *)
-module TRELLIS_SLICE(
-	input A0, B0, C0, D0,
-	input A1, B1, C1, D1,
-	input M0, M1,
-	input FCI, FXA, FXB,
-
-	input CLK, LSR, CE,
-	input DI0, DI1,
-
-	input WD0, WD1,
-	input WAD0, WAD1, WAD2, WAD3,
-	input WRE, WCK,
-
-	output F0, Q0,
-	output F1, Q1,
-	output FCO, OFX0, OFX1,
-
-    output WDO0, WDO1, WDO2, WDO3,
-    output WADO0, WADO1, WADO2, WADO3
-);
-
-parameter MODE = "LOGIC";
-parameter GSR = "ENABLED";
-parameter SRMODE = "LSR_OVER_CE";
-parameter CEMUX = "1";
-parameter CLKMUX = "CLK";
-parameter LSRMUX = "LSR";
-parameter LUT0_INITVAL = 16'h0000;
-parameter LUT1_INITVAL = 16'h0000;
-parameter REG0_SD = "0";
-parameter REG1_SD = "0";
-parameter REG0_REGSET = "RESET";
-parameter REG1_REGSET = "RESET";
-parameter CCU2_INJECT1_0 = "NO";
-parameter CCU2_INJECT1_1 = "NO";
-
-endmodule
-
-(* blackbox *) (* keep *)
-module TRELLIS_IO(
-	inout B,
-	input I,
-	input T,
-	output O,
-);
-parameter DIR = "INPUT";
-
-endmodule
diff --git a/ecp5/synth/simple_map.v b/ecp5/synth/simple_map.v
deleted file mode 100644
index 550fa92c..00000000
--- a/ecp5/synth/simple_map.v
+++ /dev/null
@@ -1,68 +0,0 @@
-module \$_DFF_P_ (input D, C, output Q);
-	TRELLIS_SLICE #(
-		.MODE("LOGIC"),
-		.CLKMUX("CLK"),
-		.CEMUX("1"),
-		.REG0_SD("0"),
-		.REG0_REGSET("RESET"),
-		.SRMODE("LSR_OVER_CE"),
-		.GSR("DISABLED")
-	) _TECHMAP_REPLACE_ (
-		.CLK(C),
-		.M0(D),
-		.Q0(Q)
-	);
-endmodule
-
-module \$lut (A, Y);
-	parameter WIDTH = 0;
-	parameter LUT = 0;
-
-	input [WIDTH-1:0] A;
-	output Y;
-
-	generate
-		if (WIDTH == 1) begin
-			TRELLIS_SLICE #(
-				.MODE("LOGIC"),
-				.LUT0_INITVAL({8{LUT[1:0]}})
-			) _TECHMAP_REPLACE_ (
-				.A0(A[0]),
-				.F0(Y)
-			);
-		end
-		if (WIDTH == 2) begin
-			TRELLIS_SLICE #(
-				.MODE("LOGIC"),
-				.LUT0_INITVAL({4{LUT[3:0]}})
-			) _TECHMAP_REPLACE_ (
-				.A0(A[0]),
-				.B0(A[1]),
-				.F0(Y)
-			);
-		end
-		if (WIDTH == 3) begin
-			TRELLIS_SLICE #(
-				.MODE("LOGIC"),
-				.LUT0_INITVAL({2{LUT[7:0]}})
-			) _TECHMAP_REPLACE_ (
-				.A0(A[0]),
-				.B0(A[1]),
-				.C0(A[2]),
-				.F0(Y)
-			);
-		end
-		if (WIDTH == 4) begin
-			TRELLIS_SLICE #(
-				.MODE("LOGIC"),
-				.LUT0_INITVAL(LUT)
-			) _TECHMAP_REPLACE_ (
-				.A0(A[0]),
-				.B0(A[1]),
-				.C0(A[2]),
-				.D0(A[3]),
-				.F0(Y)
-			);
-		end
-	endgenerate
-endmodule
diff --git a/ecp5/synth/ulx3s.v b/ecp5/synth/ulx3s.v
deleted file mode 100644
index 08f6e65b..00000000
--- a/ecp5/synth/ulx3s.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top(input a_pin, output led_pin, output led2_pin, output gpio0_pin);
-
-	wire a;
-	wire led, led2;
-    wire gpio0;
-	(* BEL="X4/Y71/PIOA" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
-	(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led));
-    (* BEL="X0/Y26/PIOA" *) (* IO_TYPE="LVCMOS33" *)
-    TRELLIS_IO #(.DIR("OUTPUT")) led2_buf (.B(led2_pin), .I(led2));
-	(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
-	TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
-    assign led = a;
-    assign led2 = !a;
-
-    TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
-endmodule
diff --git a/ecp5/synth/ulx3s.ys b/ecp5/synth/ulx3s.ys
deleted file mode 100644
index d741c985..00000000
--- a/ecp5/synth/ulx3s.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog ulx3s.v
-read_verilog -lib cells.v
-synth -top top
-abc -lut 4
-techmap -map simple_map.v
-splitnets
-opt_clean
-stat
-write_json ulx3s.json
diff --git a/ecp5/synth/wire.v b/ecp5/synth/wire.v
deleted file mode 100644
index 2af68ed2..00000000
--- a/ecp5/synth/wire.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top(input a_pin, output [3:0] led_pin);
-
-	wire a;
-	wire [3:0] led;
-
-	TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
-	TRELLIS_IO #(.DIR("OUTPUT")) led_buf [3:0] (.B(led_pin), .I(led));
-
-    //assign led[0] = !a;
-    always @(posedge a) led[0] <= !led[0];
-endmodule
diff --git a/ecp5/synth/wire.ys b/ecp5/synth/wire.ys
deleted file mode 100644
index f916588b..00000000
--- a/ecp5/synth/wire.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog wire.v
-read_verilog -lib cells.v
-synth -top top
-abc -lut 4
-techmap -map simple_map.v
-splitnets
-opt_clean
-stat
-write_json wire.json