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| author | David Shah <davey1576@gmail.com> | 2018-07-12 10:09:56 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-07-12 10:09:56 +0200 |
| commit | 9e06954edb1071b4ef2e7ebc525d8c6de42d0fc3 (patch) | |
| tree | 4132ddeaed634bd041ebc500d46cb7f70493bf59 /ecp5/synth | |
| parent | b58d665b43dae745b6aee4c56106a45f48379220 (diff) | |
| download | nextpnr-9e06954edb1071b4ef2e7ebc525d8c6de42d0fc3.tar.gz nextpnr-9e06954edb1071b4ef2e7ebc525d8c6de42d0fc3.tar.bz2 nextpnr-9e06954edb1071b4ef2e7ebc525d8c6de42d0fc3.zip | |
ecp5: Improving SLICE bel
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ecp5/synth')
| -rw-r--r-- | ecp5/synth/cells.v | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/ecp5/synth/cells.v b/ecp5/synth/cells.v index d2c6d560..353b8ada 100644 --- a/ecp5/synth/cells.v +++ b/ecp5/synth/cells.v @@ -4,10 +4,20 @@ module TRELLIS_SLICE( input A1, B1, C1, D1, input M0, M1, input FCI, FXA, FXB, + input CLK, LSR, CE, + input DI0, DI1, + + input WD0, WD1, + input WAD0, WAD1, WAD2, WAD3, + input WRE, WCK, + output F0, Q0, output F1, Q1, - output FCO, OFX0, OFX1 + output FCO, OFX0, OFX1, + + output WDO0, WDO1, WDO2, WDO3, + output WADO0, WADO1, WADO2, WADO3 ); parameter MODE = "LOGIC"; |