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authorMiodrag Milanovic <mmicko@gmail.com>2019-10-11 08:15:02 +0200
committerMiodrag Milanovic <mmicko@gmail.com>2019-10-20 09:41:48 +0200
commit1ae64d7bf53cb988003fa9b3eff1f36c30d4d50d (patch)
treedb23da7e93fbc7348f654111ba9f552572e67b63 /ecp5/gfx.h
parentd1dc2c3a5f4fc1d737eeac7d0fb9c87bf89c392b (diff)
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Display rest of slice input wires
Diffstat (limited to 'ecp5/gfx.h')
-rw-r--r--ecp5/gfx.h62
1 files changed, 61 insertions, 1 deletions
diff --git a/ecp5/gfx.h b/ecp5/gfx.h
index c8d77766..00d131e8 100644
--- a/ecp5/gfx.h
+++ b/ecp5/gfx.h
@@ -50,7 +50,67 @@ const float io_cell_h_pitch = 0.125;
enum GfxTileWireId
{
TILE_WIRE_NONE,
-
+
+ TILE_WIRE_D7_SLICE,
+ TILE_WIRE_C7_SLICE,
+ TILE_WIRE_B7_SLICE,
+ TILE_WIRE_A7_SLICE,
+ TILE_WIRE_D6_SLICE,
+ TILE_WIRE_C6_SLICE,
+ TILE_WIRE_B6_SLICE,
+ TILE_WIRE_A6_SLICE,
+ TILE_WIRE_DI7_SLICE,
+ TILE_WIRE_DI6_SLICE,
+ TILE_WIRE_M7_SLICE,
+ TILE_WIRE_M6_SLICE,
+ TILE_WIRE_FXBD_SLICE,
+ TILE_WIRE_FXAD_SLICE,
+ TILE_WIRE_WRE3_SLICE_DUMMY,
+ TILE_WIRE_WCK3_SLICE_DUMMY,
+ TILE_WIRE_CE3_SLICE,
+ TILE_WIRE_LSR3_SLICE,
+ TILE_WIRE_CLK3_SLICE,
+
+ TILE_WIRE_D5_SLICE,
+ TILE_WIRE_C5_SLICE,
+ TILE_WIRE_B5_SLICE,
+ TILE_WIRE_A5_SLICE,
+ TILE_WIRE_D4_SLICE,
+ TILE_WIRE_C4_SLICE,
+ TILE_WIRE_B4_SLICE,
+ TILE_WIRE_A4_SLICE,
+ TILE_WIRE_DI5_SLICE,
+ TILE_WIRE_DI4_SLICE,
+ TILE_WIRE_M5_SLICE,
+ TILE_WIRE_M4_SLICE,
+ TILE_WIRE_FXBC_SLICE,
+ TILE_WIRE_FXAC_SLICE,
+ TILE_WIRE_WRE2_SLICE_DUMMY,
+ TILE_WIRE_WCK2_SLICE_DUMMY,
+ TILE_WIRE_CE2_SLICE,
+ TILE_WIRE_LSR2_SLICE,
+ TILE_WIRE_CLK2_SLICE,
+
+ TILE_WIRE_D3_SLICE,
+ TILE_WIRE_C3_SLICE,
+ TILE_WIRE_B3_SLICE,
+ TILE_WIRE_A3_SLICE,
+ TILE_WIRE_D2_SLICE,
+ TILE_WIRE_C2_SLICE,
+ TILE_WIRE_B2_SLICE,
+ TILE_WIRE_A2_SLICE,
+ TILE_WIRE_DI3_SLICE,
+ TILE_WIRE_DI2_SLICE,
+ TILE_WIRE_M3_SLICE,
+ TILE_WIRE_M2_SLICE,
+ TILE_WIRE_FXBB_SLICE,
+ TILE_WIRE_FXAB_SLICE,
+ TILE_WIRE_WRE1_SLICE,
+ TILE_WIRE_WCK1_SLICE,
+ TILE_WIRE_CE1_SLICE,
+ TILE_WIRE_LSR1_SLICE,
+ TILE_WIRE_CLK1_SLICE,
+
TILE_WIRE_D1_SLICE,
TILE_WIRE_C1_SLICE,
TILE_WIRE_B1_SLICE,