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authorDavid Shah <davey1576@gmail.com>2018-10-17 11:14:27 +0100
committerGitHub <noreply@github.com>2018-10-17 11:14:27 +0100
commitb53a4862db99e41f16c06425f314a1a398a21985 (patch)
treedbe277f6d9487eab64715e4c14ce9be230820c38 /ecp5/config.h
parent529a595157a2eef24f8529b0de0c504a40ed503b (diff)
parent1cde2080902c25d2a59e8ebb5b0b23a90f693e8e (diff)
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Merge pull request #89 from YosysHQ/ecp5_bram
ECP5 BRAM support
Diffstat (limited to 'ecp5/config.h')
-rw-r--r--ecp5/config.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/ecp5/config.h b/ecp5/config.h
index 3d2ef971..8b38de5d 100644
--- a/ecp5/config.h
+++ b/ecp5/config.h
@@ -98,6 +98,14 @@ std::ostream &operator<<(std::ostream &out, const TileConfig &tc);
std::istream &operator>>(std::istream &in, TileConfig &ce);
+// A group of tiles to configure at once for a particular feature that is split across tiles
+// TileGroups are currently for non-routing configuration only
+struct TileGroup
+{
+ std::vector<std::string> tiles;
+ TileConfig config;
+};
+
// This represents the configuration of a chip at a high level
class ChipConfig
{
@@ -105,6 +113,8 @@ class ChipConfig
std::string chip_name;
std::vector<std::string> metadata;
std::map<std::string, TileConfig> tiles;
+ std::vector<TileGroup> tilegroups;
+ std::map<uint16_t, std::vector<uint16_t>> bram_data;
};
std::ostream &operator<<(std::ostream &out, const ChipConfig &cc);