refactor: Use constids instead of id("..")

Signed-off-by: gatecat <gatecat@ds0.me>

1 files changed, 213 insertions, 213 deletions

diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 18d9107f..6d88af75 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -47,129 +47,129 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         }
     };
 
-    if (type == ctx->id("TRELLIS_SLICE")) {
-        new_cell->params[ctx->id("MODE")] = std::string("LOGIC");
-        new_cell->params[ctx->id("GSR")] = std::string("DISABLED");
-        new_cell->params[ctx->id("SRMODE")] = std::string("LSR_OVER_CE");
-        new_cell->params[ctx->id("CEMUX")] = std::string("1");
-        new_cell->params[ctx->id("CLKMUX")] = std::string("CLK");
-        new_cell->params[ctx->id("LSRMUX")] = std::string("LSR");
-        new_cell->params[ctx->id("LUT0_INITVAL")] = Property(0, 16);
-        new_cell->params[ctx->id("LUT1_INITVAL")] = Property(0, 16);
-        new_cell->params[ctx->id("REG0_SD")] = std::string("0");
-        new_cell->params[ctx->id("REG1_SD")] = std::string("0");
-        new_cell->params[ctx->id("REG0_REGSET")] = std::string("RESET");
-        new_cell->params[ctx->id("REG1_REGSET")] = std::string("RESET");
-        new_cell->params[ctx->id("CCU2_INJECT1_0")] = std::string("NO");
-        new_cell->params[ctx->id("CCU2_INJECT1_1")] = std::string("NO");
-        new_cell->params[ctx->id("WREMUX")] = std::string("WRE");
-
-        new_cell->addInput(ctx->id("A0"));
-        new_cell->addInput(ctx->id("B0"));
-        new_cell->addInput(ctx->id("C0"));
-        new_cell->addInput(ctx->id("D0"));
-
-        new_cell->addInput(ctx->id("A1"));
-        new_cell->addInput(ctx->id("B1"));
-        new_cell->addInput(ctx->id("C1"));
-        new_cell->addInput(ctx->id("D1"));
-
-        new_cell->addInput(ctx->id("M0"));
-        new_cell->addInput(ctx->id("M1"));
-
-        new_cell->addInput(ctx->id("FCI"));
-        new_cell->addInput(ctx->id("FXA"));
-        new_cell->addInput(ctx->id("FXB"));
-
-        new_cell->addInput(ctx->id("CLK"));
-        new_cell->addInput(ctx->id("LSR"));
-        new_cell->addInput(ctx->id("CE"));
-
-        new_cell->addInput(ctx->id("DI0"));
-        new_cell->addInput(ctx->id("DI1"));
-
-        new_cell->addInput(ctx->id("WD0"));
-        new_cell->addInput(ctx->id("WD1"));
-        new_cell->addInput(ctx->id("WAD0"));
-        new_cell->addInput(ctx->id("WAD1"));
-        new_cell->addInput(ctx->id("WAD2"));
-        new_cell->addInput(ctx->id("WAD3"));
-        new_cell->addInput(ctx->id("WRE"));
-        new_cell->addInput(ctx->id("WCK"));
-
-        new_cell->addOutput(ctx->id("F0"));
-        new_cell->addOutput(ctx->id("Q0"));
-        new_cell->addOutput(ctx->id("F1"));
-        new_cell->addOutput(ctx->id("Q1"));
-
-        new_cell->addOutput(ctx->id("FCO"));
-        new_cell->addOutput(ctx->id("OFX0"));
-        new_cell->addOutput(ctx->id("OFX1"));
-
-        new_cell->addOutput(ctx->id("WDO0"));
-        new_cell->addOutput(ctx->id("WDO1"));
-        new_cell->addOutput(ctx->id("WDO2"));
-        new_cell->addOutput(ctx->id("WDO3"));
-        new_cell->addOutput(ctx->id("WADO0"));
-        new_cell->addOutput(ctx->id("WADO1"));
-        new_cell->addOutput(ctx->id("WADO2"));
-        new_cell->addOutput(ctx->id("WADO3"));
-    } else if (type == ctx->id("TRELLIS_IO")) {
-        new_cell->params[ctx->id("DIR")] = std::string("INPUT");
-        new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33");
-        new_cell->params[ctx->id("DATAMUX_ODDR")] = std::string("PADDO");
-        new_cell->params[ctx->id("DATAMUX_MDDR")] = std::string("PADDO");
-
-        new_cell->addInout(ctx->id("B"));
-        new_cell->addInput(ctx->id("I"));
-        new_cell->addInput(ctx->id("T"));
-        new_cell->addOutput(ctx->id("O"));
-
-        new_cell->addInput(ctx->id("IOLDO"));
-        new_cell->addInput(ctx->id("IOLTO"));
-
-    } else if (type == ctx->id("LUT4")) {
-        new_cell->params[ctx->id("INIT")] = Property(0, 16);
-
-        new_cell->addInput(ctx->id("A"));
-        new_cell->addInput(ctx->id("B"));
-        new_cell->addInput(ctx->id("C"));
-        new_cell->addInput(ctx->id("D"));
-        new_cell->addOutput(ctx->id("Z"));
-    } else if (type == ctx->id("CCU2C")) {
-        new_cell->params[ctx->id("INIT0")] = Property(0, 16);
-        new_cell->params[ctx->id("INIT1")] = Property(0, 16);
-        new_cell->params[ctx->id("INJECT1_0")] = std::string("YES");
-        new_cell->params[ctx->id("INJECT1_1")] = std::string("YES");
-
-        new_cell->addInput(ctx->id("CIN"));
-
-        new_cell->addInput(ctx->id("A0"));
-        new_cell->addInput(ctx->id("B0"));
-        new_cell->addInput(ctx->id("C0"));
-        new_cell->addInput(ctx->id("D0"));
-
-        new_cell->addInput(ctx->id("A1"));
-        new_cell->addInput(ctx->id("B1"));
-        new_cell->addInput(ctx->id("C1"));
-        new_cell->addInput(ctx->id("D1"));
-
-        new_cell->addOutput(ctx->id("S0"));
-        new_cell->addOutput(ctx->id("S1"));
-        new_cell->addOutput(ctx->id("COUT"));
-
-    } else if (type == ctx->id("DCCA")) {
-        new_cell->addInput(ctx->id("CLKI"));
-        new_cell->addOutput(ctx->id("CLKO"));
-        new_cell->addInput(ctx->id("CE"));
+    if (type == id_TRELLIS_SLICE) {
+        new_cell->params[id_MODE] = std::string("LOGIC");
+        new_cell->params[id_GSR] = std::string("DISABLED");
+        new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE");
+        new_cell->params[id_CEMUX] = std::string("1");
+        new_cell->params[id_CLKMUX] = std::string("CLK");
+        new_cell->params[id_LSRMUX] = std::string("LSR");
+        new_cell->params[id_LUT0_INITVAL] = Property(0, 16);
+        new_cell->params[id_LUT1_INITVAL] = Property(0, 16);
+        new_cell->params[id_REG0_SD] = std::string("0");
+        new_cell->params[id_REG1_SD] = std::string("0");
+        new_cell->params[id_REG0_REGSET] = std::string("RESET");
+        new_cell->params[id_REG1_REGSET] = std::string("RESET");
+        new_cell->params[id_CCU2_INJECT1_0] = std::string("NO");
+        new_cell->params[id_CCU2_INJECT1_1] = std::string("NO");
+        new_cell->params[id_WREMUX] = std::string("WRE");
+
+        new_cell->addInput(id_A0);
+        new_cell->addInput(id_B0);
+        new_cell->addInput(id_C0);
+        new_cell->addInput(id_D0);
+
+        new_cell->addInput(id_A1);
+        new_cell->addInput(id_B1);
+        new_cell->addInput(id_C1);
+        new_cell->addInput(id_D1);
+
+        new_cell->addInput(id_M0);
+        new_cell->addInput(id_M1);
+
+        new_cell->addInput(id_FCI);
+        new_cell->addInput(id_FXA);
+        new_cell->addInput(id_FXB);
+
+        new_cell->addInput(id_CLK);
+        new_cell->addInput(id_LSR);
+        new_cell->addInput(id_CE);
+
+        new_cell->addInput(id_DI0);
+        new_cell->addInput(id_DI1);
+
+        new_cell->addInput(id_WD0);
+        new_cell->addInput(id_WD1);
+        new_cell->addInput(id_WAD0);
+        new_cell->addInput(id_WAD1);
+        new_cell->addInput(id_WAD2);
+        new_cell->addInput(id_WAD3);
+        new_cell->addInput(id_WRE);
+        new_cell->addInput(id_WCK);
+
+        new_cell->addOutput(id_F0);
+        new_cell->addOutput(id_Q0);
+        new_cell->addOutput(id_F1);
+        new_cell->addOutput(id_Q1);
+
+        new_cell->addOutput(id_FCO);
+        new_cell->addOutput(id_OFX0);
+        new_cell->addOutput(id_OFX1);
+
+        new_cell->addOutput(id_WDO0);
+        new_cell->addOutput(id_WDO1);
+        new_cell->addOutput(id_WDO2);
+        new_cell->addOutput(id_WDO3);
+        new_cell->addOutput(id_WADO0);
+        new_cell->addOutput(id_WADO1);
+        new_cell->addOutput(id_WADO2);
+        new_cell->addOutput(id_WADO3);
+    } else if (type == id_TRELLIS_IO) {
+        new_cell->params[id_DIR] = std::string("INPUT");
+        new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
+        new_cell->params[id_DATAMUX_ODDR] = std::string("PADDO");
+        new_cell->params[id_DATAMUX_MDDR] = std::string("PADDO");
+
+        new_cell->addInout(id_B);
+        new_cell->addInput(id_I);
+        new_cell->addInput(id_T);
+        new_cell->addOutput(id_O);
+
+        new_cell->addInput(id_IOLDO);
+        new_cell->addInput(id_IOLTO);
+
+    } else if (type == id_LUT4) {
+        new_cell->params[id_INIT] = Property(0, 16);
+
+        new_cell->addInput(id_A);
+        new_cell->addInput(id_B);
+        new_cell->addInput(id_C);
+        new_cell->addInput(id_D);
+        new_cell->addOutput(id_Z);
+    } else if (type == id_CCU2C) {
+        new_cell->params[id_INIT0] = Property(0, 16);
+        new_cell->params[id_INIT1] = Property(0, 16);
+        new_cell->params[id_INJECT1_0] = std::string("YES");
+        new_cell->params[id_INJECT1_1] = std::string("YES");
+
+        new_cell->addInput(id_CIN);
+
+        new_cell->addInput(id_A0);
+        new_cell->addInput(id_B0);
+        new_cell->addInput(id_C0);
+        new_cell->addInput(id_D0);
+
+        new_cell->addInput(id_A1);
+        new_cell->addInput(id_B1);
+        new_cell->addInput(id_C1);
+        new_cell->addInput(id_D1);
+
+        new_cell->addOutput(id_S0);
+        new_cell->addOutput(id_S1);
+        new_cell->addOutput(id_COUT);
+
+    } else if (type == id_DCCA) {
+        new_cell->addInput(id_CLKI);
+        new_cell->addOutput(id_CLKO);
+        new_cell->addInput(id_CE);
     } else if (type == id_IOLOGIC || type == id_SIOLOGIC) {
-        new_cell->params[ctx->id("MODE")] = std::string("NONE");
-        new_cell->params[ctx->id("GSR")] = std::string("DISABLED");
-        new_cell->params[ctx->id("CLKIMUX")] = std::string("CLK");
-        new_cell->params[ctx->id("CLKOMUX")] = std::string("CLK");
-        new_cell->params[ctx->id("LSRIMUX")] = std::string("0");
-        new_cell->params[ctx->id("LSROMUX")] = std::string("0");
-        new_cell->params[ctx->id("LSRMUX")] = std::string("LSR");
+        new_cell->params[id_MODE] = std::string("NONE");
+        new_cell->params[id_GSR] = std::string("DISABLED");
+        new_cell->params[id_CLKIMUX] = std::string("CLK");
+        new_cell->params[id_CLKOMUX] = std::string("CLK");
+        new_cell->params[id_LSRIMUX] = std::string("0");
+        new_cell->params[id_LSROMUX] = std::string("0");
+        new_cell->params[id_LSRMUX] = std::string("LSR");
 
         new_cell->params[ctx->id("DELAY.OUTDEL")] = std::string("DISABLED");
         new_cell->params[ctx->id("DELAY.DEL_VALUE")] = Property(0, 7);
@@ -183,7 +183,7 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
             new_cell->params[ctx->id("MODDRX.MODE")] = std::string("NONE");
             new_cell->params[ctx->id("MTDDRX.MODE")] = std::string("NONE");
 
-            new_cell->params[ctx->id("IOLTOMUX")] = std::string("NONE");
+            new_cell->params[id_IOLTOMUX] = std::string("NONE");
             new_cell->params[ctx->id("MTDDRX.DQSW_INVERT")] = std::string("DISABLED");
             new_cell->params[ctx->id("MTDDRX.REGSET")] = std::string("RESET");
 
@@ -192,8 +192,8 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         // Just copy ports from the Bel
         copy_bel_ports();
     } else if (type == id_TRELLIS_ECLKBUF) {
-        new_cell->addInput(ctx->id("ECLKI"));
-        new_cell->addOutput(ctx->id("ECLKO"));
+        new_cell->addInput(id_ECLKI);
+        new_cell->addOutput(id_ECLKO);
     } else {
         log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
     }
@@ -225,38 +225,38 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ff->hierpath;
-    bool has_ff = lc->ports.at(ctx->id("Q0")).net != nullptr || lc->ports.at(ctx->id("Q1")).net != nullptr;
+    bool has_ff = lc->ports.at(id_Q0).net != nullptr || lc->ports.at(id_Q1).net != nullptr;
     std::string reg = "REG" + std::to_string(index);
-    set_param_safe(has_ff, lc, ctx->id("SRMODE"), str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
-    set_param_safe(has_ff, lc, ctx->id("GSR"), str_or_default(ff->params, ctx->id("GSR"), "DISABLED"));
-    set_param_safe(has_ff, lc, ctx->id("CEMUX"), str_or_default(ff->params, ctx->id("CEMUX"), "1"));
-    set_param_safe(has_ff, lc, ctx->id("LSRMUX"), str_or_default(ff->params, ctx->id("LSRMUX"), "LSR"));
-    set_param_safe(has_ff, lc, ctx->id("CLKMUX"), str_or_default(ff->params, ctx->id("CLKMUX"), "CLK"));
+    set_param_safe(has_ff, lc, id_SRMODE, str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE"));
+    set_param_safe(has_ff, lc, id_GSR, str_or_default(ff->params, id_GSR, "DISABLED"));
+    set_param_safe(has_ff, lc, id_CEMUX, str_or_default(ff->params, id_CEMUX, "1"));
+    set_param_safe(has_ff, lc, id_LSRMUX, str_or_default(ff->params, id_LSRMUX, "LSR"));
+    set_param_safe(has_ff, lc, id_CLKMUX, str_or_default(ff->params, id_CLKMUX, "CLK"));
 
     lc->params[ctx->id(reg + "_SD")] = std::string(driven_by_lut ? "1" : "0");
-    lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, ctx->id("REGSET"), "RESET");
-    lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, ctx->id("LSRMODE"), "LSR");
-    replace_port_safe(has_ff, ff, ctx->id("CLK"), lc, ctx->id("CLK"));
-    if (ff->ports.find(ctx->id("LSR")) != ff->ports.end())
-        replace_port_safe(has_ff, ff, ctx->id("LSR"), lc, ctx->id("LSR"));
-    if (ff->ports.find(ctx->id("CE")) != ff->ports.end())
-        replace_port_safe(has_ff, ff, ctx->id("CE"), lc, ctx->id("CE"));
-
-    replace_port(ff, ctx->id("Q"), lc, ctx->id("Q" + std::to_string(index)));
-    if (get_net_or_empty(ff, ctx->id("M")) != nullptr) {
+    lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, id_REGSET, "RESET");
+    lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, id_LSRMODE, "LSR");
+    replace_port_safe(has_ff, ff, id_CLK, lc, id_CLK);
+    if (ff->ports.find(id_LSR) != ff->ports.end())
+        replace_port_safe(has_ff, ff, id_LSR, lc, id_LSR);
+    if (ff->ports.find(id_CE) != ff->ports.end())
+        replace_port_safe(has_ff, ff, id_CE, lc, id_CE);
+
+    replace_port(ff, id_Q, lc, ctx->id("Q" + std::to_string(index)));
+    if (get_net_or_empty(ff, id_M) != nullptr) {
         // PRLD FFs that use both M and DI
         NPNR_ASSERT(!driven_by_lut);
         // As M is used; must route DI through a new LUT
         lc->params[ctx->id(reg + "_SD")] = std::string("1");
         lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = Property(0xFF00, 16);
-        replace_port(ff, ctx->id("DI"), lc, ctx->id("D" + std::to_string(index)));
-        replace_port(ff, ctx->id("M"), lc, ctx->id("M" + std::to_string(index)));
+        replace_port(ff, id_DI, lc, ctx->id("D" + std::to_string(index)));
+        replace_port(ff, id_M, lc, ctx->id("M" + std::to_string(index)));
         connect_ports(ctx, lc, ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index)));
     } else {
         if (driven_by_lut) {
-            replace_port(ff, ctx->id("DI"), lc, ctx->id("DI" + std::to_string(index)));
+            replace_port(ff, id_DI, lc, ctx->id("DI" + std::to_string(index)));
         } else {
-            replace_port(ff, ctx->id("DI"), lc, ctx->id("M" + std::to_string(index)));
+            replace_port(ff, id_DI, lc, ctx->id("M" + std::to_string(index)));
         }
     }
 }
@@ -266,62 +266,62 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
     if (lc->hierpath == IdString())
         lc->hierpath = lut->hierpath;
     lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] =
-            get_or_default(lut->params, ctx->id("INIT"), Property(0, 16));
-    replace_port(lut, ctx->id("A"), lc, ctx->id("A" + std::to_string(index)));
-    replace_port(lut, ctx->id("B"), lc, ctx->id("B" + std::to_string(index)));
-    replace_port(lut, ctx->id("C"), lc, ctx->id("C" + std::to_string(index)));
-    replace_port(lut, ctx->id("D"), lc, ctx->id("D" + std::to_string(index)));
-    replace_port(lut, ctx->id("Z"), lc, ctx->id("F" + std::to_string(index)));
+            get_or_default(lut->params, id_INIT, Property(0, 16));
+    replace_port(lut, id_A, lc, ctx->id("A" + std::to_string(index)));
+    replace_port(lut, id_B, lc, ctx->id("B" + std::to_string(index)));
+    replace_port(lut, id_C, lc, ctx->id("C" + std::to_string(index)));
+    replace_port(lut, id_D, lc, ctx->id("D" + std::to_string(index)));
+    replace_port(lut, id_Z, lc, ctx->id("F" + std::to_string(index)));
 }
 
 void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ccu->hierpath;
-    lc->params[ctx->id("MODE")] = std::string("CCU2");
-    lc->params[ctx->id("LUT0_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT0"), Property(0, 16));
-    lc->params[ctx->id("LUT1_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT1"), Property(0, 16));
+    lc->params[id_MODE] = std::string("CCU2");
+    lc->params[id_LUT0_INITVAL] = get_or_default(ccu->params, id_INIT0, Property(0, 16));
+    lc->params[id_LUT1_INITVAL] = get_or_default(ccu->params, id_INIT1, Property(0, 16));
 
-    lc->params[ctx->id("CCU2_INJECT1_0")] = str_or_default(ccu->params, ctx->id("INJECT1_0"), "YES");
-    lc->params[ctx->id("CCU2_INJECT1_1")] = str_or_default(ccu->params, ctx->id("INJECT1_1"), "YES");
+    lc->params[id_CCU2_INJECT1_0] = str_or_default(ccu->params, id_INJECT1_0, "YES");
+    lc->params[id_CCU2_INJECT1_1] = str_or_default(ccu->params, id_INJECT1_1, "YES");
 
-    replace_port(ccu, ctx->id("CIN"), lc, ctx->id("FCI"));
+    replace_port(ccu, id_CIN, lc, id_FCI);
 
-    replace_port(ccu, ctx->id("A0"), lc, ctx->id("A0"));
-    replace_port(ccu, ctx->id("B0"), lc, ctx->id("B0"));
-    replace_port(ccu, ctx->id("C0"), lc, ctx->id("C0"));
-    replace_port(ccu, ctx->id("D0"), lc, ctx->id("D0"));
+    replace_port(ccu, id_A0, lc, id_A0);
+    replace_port(ccu, id_B0, lc, id_B0);
+    replace_port(ccu, id_C0, lc, id_C0);
+    replace_port(ccu, id_D0, lc, id_D0);
 
-    replace_port(ccu, ctx->id("A1"), lc, ctx->id("A1"));
-    replace_port(ccu, ctx->id("B1"), lc, ctx->id("B1"));
-    replace_port(ccu, ctx->id("C1"), lc, ctx->id("C1"));
-    replace_port(ccu, ctx->id("D1"), lc, ctx->id("D1"));
+    replace_port(ccu, id_A1, lc, id_A1);
+    replace_port(ccu, id_B1, lc, id_B1);
+    replace_port(ccu, id_C1, lc, id_C1);
+    replace_port(ccu, id_D1, lc, id_D1);
 
-    replace_port(ccu, ctx->id("S0"), lc, ctx->id("F0"));
-    replace_port(ccu, ctx->id("S1"), lc, ctx->id("F1"));
+    replace_port(ccu, id_S0, lc, id_F0);
+    replace_port(ccu, id_S1, lc, id_F1);
 
-    replace_port(ccu, ctx->id("COUT"), lc, ctx->id("FCO"));
+    replace_port(ccu, id_COUT, lc, id_FCO);
 }
 
 void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ram->hierpath;
-    lc->params[ctx->id("MODE")] = std::string("RAMW");
-    replace_port(ram, ctx->id("WAD[0]"), lc, ctx->id("D0"));
-    replace_port(ram, ctx->id("WAD[1]"), lc, ctx->id("B0"));
-    replace_port(ram, ctx->id("WAD[2]"), lc, ctx->id("C0"));
-    replace_port(ram, ctx->id("WAD[3]"), lc, ctx->id("A0"));
-
-    replace_port(ram, ctx->id("DI[0]"), lc, ctx->id("C1"));
-    replace_port(ram, ctx->id("DI[1]"), lc, ctx->id("A1"));
-    replace_port(ram, ctx->id("DI[2]"), lc, ctx->id("D1"));
-    replace_port(ram, ctx->id("DI[3]"), lc, ctx->id("B1"));
+    lc->params[id_MODE] = std::string("RAMW");
+    replace_port(ram, ctx->id("WAD[0]"), lc, id_D0);
+    replace_port(ram, ctx->id("WAD[1]"), lc, id_B0);
+    replace_port(ram, ctx->id("WAD[2]"), lc, id_C0);
+    replace_port(ram, ctx->id("WAD[3]"), lc, id_A0);
+
+    replace_port(ram, ctx->id("DI[0]"), lc, id_C1);
+    replace_port(ram, ctx->id("DI[1]"), lc, id_A1);
+    replace_port(ram, ctx->id("DI[2]"), lc, id_D1);
+    replace_port(ram, ctx->id("DI[3]"), lc, id_B1);
 }
 
 static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
 {
-    auto init_prop = get_or_default(ram->params, ctx->id("INITVAL"), Property(0, 64));
+    auto init_prop = get_or_default(ram->params, id_INITVAL, Property(0, 64));
     NPNR_ASSERT(!init_prop.is_string);
     const std::string &idata = init_prop.str;
     NPNR_ASSERT(idata.length() == 64);
@@ -340,9 +340,9 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
 {
     if (lc->hierpath == IdString())
         lc->hierpath = ram->hierpath;
-    lc->params[ctx->id("MODE")] = std::string("DPRAM");
-    lc->params[ctx->id("WREMUX")] = str_or_default(ram->params, ctx->id("WREMUX"), "WRE");
-    lc->params[ctx->id("WCKMUX")] = str_or_default(ram->params, ctx->id("WCKMUX"), "WCK");
+    lc->params[id_MODE] = std::string("DPRAM");
+    lc->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
+    lc->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
 
     unsigned permuted_init0 = 0, permuted_init1 = 0;
     unsigned init0 = get_dram_init(ctx, ram, index * 2), init1 = get_dram_init(ctx, ram, index * 2 + 1);
@@ -363,30 +363,30 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
             permuted_init1 |= (1 << i);
     }
 
-    lc->params[ctx->id("LUT0_INITVAL")] = Property(permuted_init0, 16);
-    lc->params[ctx->id("LUT1_INITVAL")] = Property(permuted_init1, 16);
+    lc->params[id_LUT0_INITVAL] = Property(permuted_init0, 16);
+    lc->params[id_LUT1_INITVAL] = Property(permuted_init1, 16);
 
     if (ram->ports.count(ctx->id("RAD[0]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D1);
     }
     if (ram->ports.count(ctx->id("RAD[1]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B1);
     }
     if (ram->ports.count(ctx->id("RAD[2]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C1);
     }
     if (ram->ports.count(ctx->id("RAD[3]"))) {
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A0"));
-        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A1"));
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A0);
+        connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A1);
     }
 
-    if (ram->ports.count(ctx->id("WRE")))
-        connect_port(ctx, ram->ports.at(ctx->id("WRE")).net, lc, ctx->id("WRE"));
-    if (ram->ports.count(ctx->id("WCK")))
-        connect_port(ctx, ram->ports.at(ctx->id("WCK")).net, lc, ctx->id("WCK"));
+    if (ram->ports.count(id_WRE))
+        connect_port(ctx, ram->ports.at(id_WRE).net, lc, id_WRE);
+    if (ram->ports.count(id_WCK))
+        connect_port(ctx, ram->ports.at(id_WCK).net, lc, id_WCK);
 
     connect_ports(ctx, ramw, id_WADO0, lc, id_WAD0);
     connect_ports(ctx, ramw, id_WADO1, lc, id_WAD1);
@@ -415,26 +415,26 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
                 pool<IdString> &todelete_cells)
 {
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
-        trio->params[ctx->id("DIR")] = std::string("INPUT");
-        replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+        trio->params[id_DIR] = std::string("INPUT");
+        replace_port(nxio, id_O, trio, id_O);
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
-        trio->params[ctx->id("DIR")] = std::string("OUTPUT");
-        replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
+        trio->params[id_DIR] = std::string("OUTPUT");
+        replace_port(nxio, id_I, trio, id_I);
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
-        NetInfo *i = get_net_or_empty(nxio, ctx->id("I"));
+        NetInfo *i = get_net_or_empty(nxio, id_I);
         if (i == nullptr || i->driver.cell == nullptr)
-            trio->params[ctx->id("DIR")] = std::string("INPUT");
+            trio->params[id_DIR] = std::string("INPUT");
         else {
             log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
-            trio->params[ctx->id("DIR")] = std::string("BIDIR");
+            trio->params[id_DIR] = std::string("BIDIR");
         }
-        replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
-        replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+        replace_port(nxio, id_I, trio, id_I);
+        replace_port(nxio, id_O, trio, id_O);
     } else {
         NPNR_ASSERT(false);
     }
-    NetInfo *donet = trio->ports.at(ctx->id("I")).net, *dinet = trio->ports.at(ctx->id("O")).net;
+    NetInfo *donet = trio->ports.at(id_I).net, *dinet = trio->ports.at(id_O).net;
 
     // Rename I/O nets to avoid conflicts
     if (donet != nullptr && donet->name == nxio->name)
@@ -458,20 +458,20 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
         ctx->net_aliases.erase(tn_netname);
         NetInfo *toplevel_net = ctx->createNet(tn_netname);
         toplevel_net->name = tn_netname;
-        connect_port(ctx, toplevel_net, trio, ctx->id("B"));
+        connect_port(ctx, toplevel_net, trio, id_B);
         ctx->ports[nxio->name].net = toplevel_net;
     }
 
     CellInfo *tbuf = net_driven_by(
             ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
-            ctx->id("Y"));
+            id_Y);
     if (tbuf) {
-        replace_port(tbuf, ctx->id("A"), trio, ctx->id("I"));
+        replace_port(tbuf, id_A, trio, id_I);
         // Need to invert E to form T
-        std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, ctx->id("LUT4"), trio->name.str(ctx) + "$invert_T");
-        replace_port(tbuf, ctx->id("E"), inv_lut.get(), ctx->id("A"));
-        inv_lut->params[ctx->id("INIT")] = Property(21845, 16);
-        connect_ports(ctx, inv_lut.get(), ctx->id("Z"), trio, ctx->id("T"));
+        std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, id_LUT4, trio->name.str(ctx) + "$invert_T");
+        replace_port(tbuf, id_E, inv_lut.get(), id_A);
+        inv_lut->params[id_INIT] = Property(21845, 16);
+        connect_ports(ctx, inv_lut.get(), id_Z, trio, id_T);
         created_cells.push_back(std::move(inv_lut));
 
         if (donet->users.size() > 1) {