Merge pull request #557 from litghost/refactor_placer_arch_api

RFC: Initial refactoring of placer API.

3 files changed, 108 insertions, 11 deletions

diff --git a/docs/archapi.md b/docs/archapi.md
index a9c38589..49183c63 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -40,6 +40,10 @@ A type representing a wire name. `WireId()` must construct a unique null-value.
 
 A type representing a pip name. `PipId()` must construct a unique null-value. Must provide `==`, `!=`, and `<` operators and a specialization for `std::hash<PipId>`.
 
+### BelBucketId
+
+A type representing a bel bucket. `BelBucketId()` must construct a unique null-value. Must provide `==`, `!=`, and `<` operators and a specialization for `std::hash<BelBucketId>`.
+
 ### GroupId
 
 A type representing a group name. `GroupId()` must construct a unique null-value. Must provide `==` and `!=` operators and a specialization for `std::hash<GroupId>`.
@@ -88,6 +92,14 @@ Get Z dimension for the specified tile for bels. All bels with at specified X an
 
 Get Z dimension for the specified tile for pips. All pips with at specified X and Y coordinates must have a Z coordinate in the range `0 .. getTileDimZ(X,Y)-1` (inclusive).
 
+Cell Methods
+-----------
+
+### const\_range\<IdString\> getCellTypes() const
+
+Get list of cell types that this architecture accepts.
+
+
 Bel Methods
 -----------
 
@@ -377,7 +389,7 @@ the given dst wire.
 This should return a low upper bound for the fastest route from `src` to `dst`.
 
 Or in other words it should assume an otherwise unused chip (thus "fastest route").
-But it only produces an estimate for that fastest route, not an exact 
+But it only produces an estimate for that fastest route, not an exact
 result, and for that estimate it is considered more acceptable to return a
 slightly too high result and it is considered less acceptable to return a
 too low result (thus "low upper bound").
@@ -463,21 +475,74 @@ Cell Delay Methods
 Returns the delay for the specified path through a cell in the `&delay` argument. The method returns
 false if there is no timing relationship from `fromPort` to `toPort`.
 
-### TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
+### TimingPortClass getPortTimingClass(const CellInfo \*cell, IdString port, int &clockInfoCount) const
 
 Return the _timing port class_ of a port. This can be a register or combinational input or output; clock input or
 output; general startpoint or endpoint; or a port ignored for timing purposes. For register ports, clockInfoCount is set
 to the number of associated _clock edges_ that can be queried by getPortClockingInfo.
 
-### TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
+### TimingClockingInfo getPortClockingInfo(const CellInfo \*cell, IdString port, int index) const
 
 Return the _clocking info_ (including port name of clock, clock polarity and setup/hold/clock-to-out times) of a
 port. Where ports have more than one clock edge associated with them (such as DDR outputs), `index` can be used to obtain
 information for all edges. `index` must be in [0, clockInfoCount), behaviour is undefined otherwise.
 
+Bel Buckets Methods
+-------------------
+
+Bel buckets are subsets of BelIds and cell types used by analytic placer to
+seperate types of bels during placement. The buckets should form an exact
+cover over all BelIds and cell types.
+
+Each bel bucket should be BelIds and cell types that are roughly
+interchangable during placement.  Typical buckets are:
+ - All LUT bels
+ - All FF bels
+ - All multipliers bels
+ - All block RAM bels
+ - etc.
+
+The bel buckets will be used during analytic placement for spreading prior to
+strict legality enforcement.  It is not required that all bels within a bucket
+are strictly equivelant.
+
+Strict legality step will enforce those differences, along with additional
+local constraints.  `isValidBelForCell`, `isValidBelForCellType`, and
+`isBelLocationValid` are used to enforce strict legality checks.
+
+### const\_range\<BelBucketId\> getBelBuckets() const
+
+Return a list of all bel buckets on the device.
+
+### IdString getBelBucketName(BelBucketId bucket) const
+
+Return the name of this bel bucket.
+
+### BelBucketId getBelBucketByName(IdString bucket\_name) const
+
+Return the BelBucketId for the specified bucket name.
+
+### BelBucketId getBelBucketForBel(BelId bel) const
+
+Returns the bucket for a particular bel.
+
+### BelBucketId getBelBucketForCell(IdString cell\_type) const
+
+Returns the bel bucket for a particular cell type.
+
+### const\_range\<BelId\> getBelsInBucket(BelBucketId bucket) const
+
+Return the list of bels within a bucket.
+
 Placer Methods
 --------------
 
+### bool isValidBelForCellType(IdString cell\_type, BelId bel) const
+
+Returns true if the given cell can be bound to the given bel.  This check
+should be fast, compared with isValidBelForCell.  This check should always
+return the same value regardless if other cells are placed within the fabric.
+
 ### bool isValidBelForCell(CellInfo \*cell, BelId bel) const
 
 Returns true if the given cell can be bound to the given bel, considering
@@ -489,7 +554,6 @@ a certain number of different clock signals allowed for a group of bels.
 Returns true if a bell in the current configuration is valid, i.e. if
 `isValidBelForCell()` would return true for the current mapping.
 
-
 ### static const std::string defaultPlacer
 
 Name of the default placement algorithm for the architecture, if
diff --git a/docs/coding.md b/docs/coding.md
index b8025f8b..5cbaef01 100644
--- a/docs/coding.md
+++ b/docs/coding.md
@@ -14,9 +14,9 @@ This document aims to provide an overview into the philosophy behind nextpnr's c
 
 An architecture in nextpnr is described first and foremost as code. The exact details are given in the [Arch API reference](archapi.md); this aims to explain the core concept.
 
-By choosing this approach; this gives architectures significant flexibility to use more advanced database representations than a simple flat database - for example deduplicated approaches that store similar tiles only once. 
+By choosing this approach; this gives architectures significant flexibility to use more advanced database representations than a simple flat database - for example deduplicated approaches that store similar tiles only once.
 
-Architectures can also implement custom algorithms for packing (or other initial netlist transformations) and specialized parts of placement and routing such as global clock networks. This is because architectures provide the `pack()`, `place()` and `route()` functions, although the latter two will normally use generic algorithms (such as HeAP and router1) to do most of the work. 
+Architectures can also implement custom algorithms for packing (or other initial netlist transformations) and specialized parts of placement and routing such as global clock networks. This is because architectures provide the `pack()`, `place()` and `route()` functions, although the latter two will normally use generic algorithms (such as HeAP and router1) to do most of the work.
 
 Another important function provided by architectures is placement validity checking. This allows the placer to check whether or not a given cell placement is valid. An example of this is for iCE40, where 8 logic cells in a tile share one clock signal - this is checked here.
 
@@ -24,13 +24,13 @@ This function allows architectures in nextpnr to do significantly less packing t
 
 Additionally to this; architectures provide functions for checking the availability and conflicts between resources (e.g. `checkBelAvail`, `checkPipAvail`, etc). This enables arbitrary constraints between resource availability to be defined, for example:
 
- - where a group of Pips share bitstream bits, only one can be used at a time
+ - where a group of pips share bitstream bits, only one can be used at a time
  - Pips that represent LUT permutation are not available when the LUT is in memory mode
- - only a certain total number of Pips in a switchbox can be used at once due to power supply limitations
+ - only a certain total number of pips in a switchbox can be used at once due to power supply limitations
 
 ## `IdString`s
 
-To avoid the high cost of using strings as identifiers directly; almost all "string" identifiers in nextpnr (such as cell names and types) use an indexed string pool type named `IdString`. Unlike Yosys, which has a global garbage collected pool, nextpnr has a per-Context pool without any garbage collection. 
+To avoid the high cost of using strings as identifiers directly; almost all "string" identifiers in nextpnr (such as cell names and types) use an indexed string pool type named `IdString`. Unlike Yosys, which has a global garbage collected pool, nextpnr has a per-Context pool without any garbage collection.
 
 `IdString`s can be created in two ways. Architectures can add `IdString`s with constant indices - allowing `IdString` constants to be provided too - using `initialize_add` at startup. See how `constids.inc` is used in iCE40 for an example of this. The main way to create `IdString`s, however, is at runtime using the `id` member function of `BaseCtx` given the string to create from (if an `IdString` of that string already exists, the existing `IdString` will be returned).
 
@@ -42,15 +42,36 @@ Packing in nextpnr could be done in two ways (if significant packing is done at
  - replacing multiple cells with a single larger cell that corresponds to a bel
  - combining smaller cells using relative placement constraints
 
-In flows with minimal packing the main task of the packer is to transform cells into common types that correspond to a bel (e.g. convert multiple flipflop primitives to a single common type with some extra parameters). The packer will also have to add relative constraints for fixed structures such as carry chains or LUT-MUX cascades.
+The packer will also have to add relative constraints for fixed structures such as carry chains or LUT-MUX cascades.
 
 There are several helper functions that are useful for developing packers and other passes that perform significant netlist modifications in `util.h`. It is often preferable to use these compared to direct modification of the netlist structures due to the "double linking" nextpnr does - e.g. when connecting a port you must update both the `net` field of the ports and the `driver`/`users` of the net.
 
+### Cell to bel mapping
+
+There is an Arch API choice when it comes to representing the relationship
+between cell types and bel types.  One option is to transform cells into
+common types that correspond to a bel (e.g. convert multiple flipflop
+primitives to a single common type with some extra parameters). In Arch APIs
+designed like this, packer transformations are required to convert input cell
+types into nextpnr specific cell types that have a 1 to 1 relationship with
+bel types.
+
+For Arch APIs of this type, the method `isValidBelForCellType` reduces to:
+
+```
+bool isValidBelForCellType(IdString cell_type, BelId bel) const {
+    return cell_type == getBelType(bel);
+}
+```
+
+The alternative is to implement a fast `isValidBelForCellType` method that
+determines if this cell type can be bound to this bel.
+
 ## Developing CAD algorithms - placement
 
 The job of the placer in nextpnr is to find a suitable bel for each cell in the design; while respecting legality and relative constraints.
 
-Placers might want to create their own indices of bels (for example, bels by type and location) to speed up the search. 
+Placers might want to create their own indices of bels (for example, bels by type and location) to speed up the search.
 
 As nextpnr allows arbitrary constraints on bels for more advanced packer-free flows and complex real-world architectures; placements must be checked for legality using `isValidBelForCell` (before placement) or `isBelLocationValid` (after placement) and the placement rejected if invalid. For analytical placement algorithms; after creating a spread-out AP solution the legality of placing each cell needs to be checked. In practice, the cost of this is fairly low as the architecture should ensure these functions are as fast as possible.
 
@@ -59,6 +80,17 @@ There are several routes for timing information in the placer:
     - sink ports can have a criticality (value between 0 and 1 where 1 is the critical path) associated with them by using `get_criticalities` and a `NetCriticalityMap`
     - `predictDelay` returns an estimated delay for a sink port based on placement information
 
+
+### Bel Buckets
+
+The bel Bucket Arch APIs can be used by an analytical placer (AP) for getting
+groups of bels and cell types placed together.  This grouping is important for
+algorithms like HeAP which typically want to do operate on subsets of the
+design for some portions of the placement.
+
+The HeAP implementation allows for multiple bel buckets to be placed on
+together, see the "cellGroups" field.
+
 ## Routing
 
 The job of the router is to ensure that the `wires` map for each net contains a complete routing tree; populated using the Arch functions to bind wires and pips. The ripup invariants in the [FAQ](faq.md) are important to bear in mind; as there may be complex constraints on the usage of wires and pips in some architectures.
diff --git a/docs/faq.md b/docs/faq.md
index 8a1b3f6a..085b2bd7 100644
--- a/docs/faq.md
+++ b/docs/faq.md
@@ -23,6 +23,7 @@ For nextpnr we are using the following terminology.
 - **Wire**: a fixed physical connection inside the FPGA between Pips and/or Bel pins.
 - **Alias**: a special automatic-on Pip to represent a permanent connection between two wires
 - **Group**: a collection of bels, pips, wires, and/or other groups
+- **BelBucket**: a collection of bels and cell types.  All of the bel buckets form a set cover of bels and cell types.
 
 ### Flow Terminology