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authorkittennbfive <58293822+kittennbfive@users.noreply.github.com>2020-09-28 14:49:35 +0000
committerGitHub <noreply@github.com>2020-09-28 14:49:35 +0000
commitb2438caec36bcd35606f16e52d28b011bba4d26b (patch)
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parent9aff6aa55c212df448477f3e28711ac3d0ee5aff (diff)
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update doc - UNTESTED on real hardware
Diffstat (limited to 'docs')
-rw-r--r--docs/constraints.md11
1 files changed, 9 insertions, 2 deletions
diff --git a/docs/constraints.md b/docs/constraints.md
index 67c8ddd7..4917b33f 100644
--- a/docs/constraints.md
+++ b/docs/constraints.md
@@ -9,11 +9,18 @@ The iCE40 architecture supports PCF constraints thus:
set_io led[0] 3
-and the ECP5 architecture supports a subset of LPF constraints:
+and the ECP5 architecture supports a subset of LPF constraints (for details see Lattice Technical Note "FPGA-TN-02032 1.3"):
LOCATE COMP "led[0]" SITE "E16";
IOBUF PORT "led[0]" IO_TYPE=LVCMOS25;
-
+ IOBUF ... DRIVE=8;
+ IOBUF ... OPENDRAIN=ON|OFF;
+ IOBUF ... TERMINATION=50;
+ IOBUF ... DIFFRESISTOR=100; //for differential IO only
+ IOBUF ... CLAMP=ON|OFF;
+ IOBUF ... PULLMODE=UP|DOWN|NONE;
+ IOBUF ... SLEWRATE=FAST|SLOW; //outputs only
+ IOBUF ... HYSTERESIS=ON|OFF;
## Absolute Placement Constraints