Make BELs/PIPs lowercase as bels/pips per review comment.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

3 files changed, 36 insertions, 36 deletions

diff --git a/docs/archapi.md b/docs/archapi.md
index f7246f08..49183c63 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -42,7 +42,7 @@ A type representing a pip name. `PipId()` must construct a unique null-value. Mu
 
 ### BelBucketId
 
-A type representing a BEL bucket. `BelBucketId()` must construct a unique null-value. Must provide `==`, `!=`, and `<` operators and a specialization for `std::hash<BelBucketId>`.
+A type representing a bel bucket. `BelBucketId()` must construct a unique null-value. Must provide `==`, `!=`, and `<` operators and a specialization for `std::hash<BelBucketId>`.
 
 ### GroupId
 
@@ -487,23 +487,23 @@ Return the _clocking info_ (including port name of clock, clock polarity and set
 port. Where ports have more than one clock edge associated with them (such as DDR outputs), `index` can be used to obtain
 information for all edges. `index` must be in [0, clockInfoCount), behaviour is undefined otherwise.
 
-BEL Buckets Methods
+Bel Buckets Methods
 -------------------
 
-BEL buckets are subsets of BelIds and cell types used by analytic placer to
-seperate types of BELs during placement. The buckets should form an exact
+Bel buckets are subsets of BelIds and cell types used by analytic placer to
+seperate types of bels during placement. The buckets should form an exact
 cover over all BelIds and cell types.
 
-Each BEL bucket should be BelIds and cell types that are roughly
+Each bel bucket should be BelIds and cell types that are roughly
 interchangable during placement.  Typical buckets are:
- - All LUT BELs
- - All FF BELs
- - All multipliers BELs
- - All block RAM BELs
+ - All LUT bels
+ - All FF bels
+ - All multipliers bels
+ - All block RAM bels
  - etc.
 
-The BEL buckets will be used during analytic placement for spreading prior to
-strict legality enforcement.  It is not required that all BELs within a bucket
+The bel buckets will be used during analytic placement for spreading prior to
+strict legality enforcement.  It is not required that all bels within a bucket
 are strictly equivelant.
 
 Strict legality step will enforce those differences, along with additional
@@ -512,11 +512,11 @@ local constraints.  `isValidBelForCell`, `isValidBelForCellType`, and
 
 ### const\_range\<BelBucketId\> getBelBuckets() const
 
-Return a list of all BEL buckets on the device.
+Return a list of all bel buckets on the device.
 
 ### IdString getBelBucketName(BelBucketId bucket) const
 
-Return the name of this BEL bucket.
+Return the name of this bel bucket.
 
 ### BelBucketId getBelBucketByName(IdString bucket\_name) const
 
@@ -524,30 +524,30 @@ Return the BelBucketId for the specified bucket name.
 
 ### BelBucketId getBelBucketForBel(BelId bel) const
 
-Returns the bucket for a particular BEL.
+Returns the bucket for a particular bel.
 
 ### BelBucketId getBelBucketForCell(IdString cell\_type) const
 
-Returns the BEL bucket for a particular cell type.
+Returns the bel bucket for a particular cell type.
 
 ### const\_range\<BelId\> getBelsInBucket(BelBucketId bucket) const
 
-Return the list of BELs within a bucket.
+Return the list of bels within a bucket.
 
 Placer Methods
 --------------
 
 ### bool isValidBelForCellType(IdString cell\_type, BelId bel) const
 
-Returns true if the given cell can be bound to the given BEL.  This check
+Returns true if the given cell can be bound to the given bel.  This check
 should be fast, compared with isValidBelForCell.  This check should always
 return the same value regardless if other cells are placed within the fabric.
 
 ### bool isValidBelForCell(CellInfo \*cell, BelId bel) const
 
-Returns true if the given cell can be bound to the given BEL, considering
+Returns true if the given cell can be bound to the given bel, considering
 other bound resources. For example, this can be used if there is only
-a certain number of different clock signals allowed for a group of BELs.
+a certain number of different clock signals allowed for a group of bels.
 
 ### bool isBelLocationValid(BelId bel) const
 
diff --git a/docs/coding.md b/docs/coding.md
index 0db269a6..5cbaef01 100644
--- a/docs/coding.md
+++ b/docs/coding.md
@@ -24,9 +24,9 @@ This function allows architectures in nextpnr to do significantly less packing t
 
 Additionally to this; architectures provide functions for checking the availability and conflicts between resources (e.g. `checkBelAvail`, `checkPipAvail`, etc). This enables arbitrary constraints between resource availability to be defined, for example:
 
- - where a group of PIPs share bitstream bits, only one can be used at a time
- - PIPs that represent LUT permutation are not available when the LUT is in memory mode
- - only a certain total number of PIPs in a switchbox can be used at once due to power supply limitations
+ - where a group of pips share bitstream bits, only one can be used at a time
+ - Pips that represent LUT permutation are not available when the LUT is in memory mode
+ - only a certain total number of pips in a switchbox can be used at once due to power supply limitations
 
 ## `IdString`s
 
@@ -39,22 +39,22 @@ Note that `IdString`s need a `Context` (or `BaseCtx`) pointer to convert them ba
 ## Developing CAD algorithms - packing
 
 Packing in nextpnr could be done in two ways (if significant packing is done at all):
- - replacing multiple cells with a single larger cell that corresponds to a BEL
+ - replacing multiple cells with a single larger cell that corresponds to a bel
  - combining smaller cells using relative placement constraints
 
 The packer will also have to add relative constraints for fixed structures such as carry chains or LUT-MUX cascades.
 
 There are several helper functions that are useful for developing packers and other passes that perform significant netlist modifications in `util.h`. It is often preferable to use these compared to direct modification of the netlist structures due to the "double linking" nextpnr does - e.g. when connecting a port you must update both the `net` field of the ports and the `driver`/`users` of the net.
 
-### Cell to BEL mapping
+### Cell to bel mapping
 
 There is an Arch API choice when it comes to representing the relationship
-between cell types and BEL types.  One option is to transform cells into
-common types that correspond to a BEL (e.g. convert multiple flipflop
+between cell types and bel types.  One option is to transform cells into
+common types that correspond to a bel (e.g. convert multiple flipflop
 primitives to a single common type with some extra parameters). In Arch APIs
 designed like this, packer transformations are required to convert input cell
 types into nextpnr specific cell types that have a 1 to 1 relationship with
-BEL types.
+bel types.
 
 For Arch APIs of this type, the method `isValidBelForCellType` reduces to:
 
@@ -65,15 +65,15 @@ bool isValidBelForCellType(IdString cell_type, BelId bel) const {
 ```
 
 The alternative is to implement a fast `isValidBelForCellType` method that
-determines if this cell type can be bound to this BEL.
+determines if this cell type can be bound to this bel.
 
 ## Developing CAD algorithms - placement
 
-The job of the placer in nextpnr is to find a suitable BEL for each cell in the design; while respecting legality and relative constraints.
+The job of the placer in nextpnr is to find a suitable bel for each cell in the design; while respecting legality and relative constraints.
 
-Placers might want to create their own indices of BELs (for example, BELs by type and location) to speed up the search.
+Placers might want to create their own indices of bels (for example, bels by type and location) to speed up the search.
 
-As nextpnr allows arbitrary constraints on BELs for more advanced packer-free flows and complex real-world architectures; placements must be checked for legality using `isValidBelForCell` (before placement) or `isBelLocationValid` (after placement) and the placement rejected if invalid. For analytical placement algorithms; after creating a spread-out AP solution the legality of placing each cell needs to be checked. In practice, the cost of this is fairly low as the architecture should ensure these functions are as fast as possible.
+As nextpnr allows arbitrary constraints on bels for more advanced packer-free flows and complex real-world architectures; placements must be checked for legality using `isValidBelForCell` (before placement) or `isBelLocationValid` (after placement) and the placement rejected if invalid. For analytical placement algorithms; after creating a spread-out AP solution the legality of placing each cell needs to be checked. In practice, the cost of this is fairly low as the architecture should ensure these functions are as fast as possible.
 
 There are several routes for timing information in the placer:
     - sink `PortRef`s have a `budget` value annotated by calling `assign_budget` which is an estimate of the maximum delay that an arc may have
@@ -81,14 +81,14 @@ There are several routes for timing information in the placer:
     - `predictDelay` returns an estimated delay for a sink port based on placement information
 
 
-### BEL Buckets
+### Bel Buckets
 
-The BEL Bucket Arch APIs can be used by an analytical placer (AP) for getting 
-groups of BELs and cell types placed together.  This grouping is important for
+The bel Bucket Arch APIs can be used by an analytical placer (AP) for getting
+groups of bels and cell types placed together.  This grouping is important for
 algorithms like HeAP which typically want to do operate on subsets of the
 design for some portions of the placement.
 
-The HeAP implementation allows for multiple BEL buckets to be placed on 
+The HeAP implementation allows for multiple bel buckets to be placed on
 together, see the "cellGroups" field.
 
 ## Routing
diff --git a/docs/faq.md b/docs/faq.md
index 14785430..085b2bd7 100644
--- a/docs/faq.md
+++ b/docs/faq.md
@@ -23,7 +23,7 @@ For nextpnr we are using the following terminology.
 - **Wire**: a fixed physical connection inside the FPGA between Pips and/or Bel pins.
 - **Alias**: a special automatic-on Pip to represent a permanent connection between two wires
 - **Group**: a collection of bels, pips, wires, and/or other groups
-- **BelBucket**: a collection of BELs and cell types.  All of the BEL buckets form a set cover of BELs and cell types.
+- **BelBucket**: a collection of bels and cell types.  All of the bel buckets form a set cover of bels and cell types.
 
 ### Flow Terminology