diff options
| author | ZipCPU <dgisselq@ieee.org> | 2018-06-07 12:04:01 -0400 |
|---|---|---|
| committer | ZipCPU <dgisselq@ieee.org> | 2018-06-07 12:04:01 -0400 |
| commit | a4f687548e31b64a7684fdfbb64ea82f46370e2a (patch) | |
| tree | 6695f8d69bacf6bc955c8fbc3699d3e287dbc5db /common | |
| parent | 37d2fc65b1af2de1282948ecdc5f1294f34c6fb5 (diff) | |
| download | nextpnr-a4f687548e31b64a7684fdfbb64ea82f46370e2a.tar.gz nextpnr-a4f687548e31b64a7684fdfbb64ea82f46370e2a.tar.bz2 nextpnr-a4f687548e31b64a7684fdfbb64ea82f46370e2a.zip | |
Adjusted info message names for rule-checker and parser
Diffstat (limited to 'common')
| -rw-r--r-- | common/rulecheck.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/common/rulecheck.cc b/common/rulecheck.cc index 11e57b8b..7443c636 100644 --- a/common/rulecheck.cc +++ b/common/rulecheck.cc @@ -5,7 +5,8 @@ bool check_all_nets_driven(Design *design) { const bool debug = false; - log_info("Verifying all cells\n"); + + log_info("Rule checker, Verifying pre-placed design\n"); for(auto cell_entry : design->cells) { CellInfo *cell = cell_entry.second; |