common: Add TimingPortClass

Signed-off-by: David Shah <davey1576@gmail.com>

1 files changed, 14 insertions, 1 deletions

diff --git a/common/nextpnr.h b/common/nextpnr.h
index 3d9a66ca..d4925a16 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -291,6 +291,19 @@ struct CellInfo : ArchCellInfo
     // parent.[xyz] := 0 when (constr_parent == nullptr)
 };
 
+enum TimingPortClass
+{
+    TMG_CLOCK_INPUT,     // Clock input to a sequential cell
+    TMG_GEN_CLOCK,       // Generated clock output (PLL, DCC, etc)
+    TMG_REGISTER_INPUT,  // Input to a register, with an associated clock (may also have comb. fanout too)
+    TMG_REGISTER_OUTPUT, // Output from a register
+    TMG_COMB_INPUT,      // Combinational input, no paths end here
+    TMG_COMB_OUTPUT,     // Combinational output, no paths start here
+    TMG_STARTPOINT,      // Unclocked primary startpoint, such as an IO cell output
+    TMG_ENDPOINT,        // Unclocked primary endpoint, such as an IO cell input
+    TMG_ASYNC,           // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis
+};
+
 struct DeterministicRNG
 {
     uint64_t rngstate;
@@ -437,7 +450,7 @@ struct BaseCtx
 
     const Context *getCtx() const { return reinterpret_cast<const Context *>(this); }
 
-    template<typename T> const char *nameOf(const T *obj)
+    template <typename T> const char *nameOf(const T *obj)
     {
         if (obj == nullptr)
             return "";