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authorMiodrag Milanovic <mmicko@gmail.com>2022-08-22 12:35:24 +0200
committerMiodrag Milanovic <mmicko@gmail.com>2022-08-22 12:35:24 +0200
commita00b997cf19c0123f46f6509b2e42142e72f1d8c (patch)
treeee1ec8ae3823de798eab71f288e3262505b9740b /common
parent1aa797b82068a6ac0691c2e6a5e2ebe91a9a7b72 (diff)
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add missing overrides
Diffstat (limited to 'common')
-rw-r--r--common/kernel/nextpnr_types.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index e4042aec..2a9062fd 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -205,9 +205,9 @@ struct RegionPlug : PseudoCell
WireId getPortWire(IdString port) const override { return port_wires.at(port); }
// TODO: partial reconfiguration region timing
- bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const { return false; }
- TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const { return TMG_IGNORE; }
- virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const { return TimingClockingInfo{}; }
+ bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const override { return false; }
+ TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const override { return TMG_IGNORE; }
+ TimingClockingInfo getPortClockingInfo(IdString port, int index) const override { return TimingClockingInfo{}; }
dict<IdString, WireId> port_wires;
Loc loc;