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authorgatecat <gatecat@ds0.me>2021-12-19 16:41:34 +0000
committergatecat <gatecat@ds0.me>2021-12-19 17:15:15 +0000
commitddb084e9a8a0cba10536951236cde824526e8071 (patch)
treed03ba5688367cb476a06b19d04ca78d0352afce3 /common/timing.cc
parent56d550733346000584b9490fac0953fe07124035 (diff)
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archapi: Use arbitrary rather than actual placement in predictDelay
This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'common/timing.cc')
-rw-r--r--common/timing.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/common/timing.cc b/common/timing.cc
index e305d82d..f30d4fc5 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -1378,7 +1378,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
auto driver_wire = ctx->getNetinfoSourceWire(net);
auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
log_info(" prediction: %f ns estimate: %f ns\n",
- ctx->getDelayNS(ctx->predictDelay(net, sink_ref)),
+ ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
auto cursor = sink_wire;
delay_t delay;