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authorClifford Wolf <clifford@clifford.at>2018-06-18 14:15:41 +0200
committerClifford Wolf <clifford@clifford.at>2018-06-18 14:15:41 +0200
commitf30d477c8129c3c189866a4bc862724d4e8d4398 (patch)
tree552fe4a537e6776ce9fbc360ceb9e5d62677385c /common/rulecheck.cc
parent2f5e9542c2d9132b2c01d4dbc8c4d2dff97c60cf (diff)
parentcbcd2ea3acaf257bf39b25a38d9f591e82a66f37 (diff)
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Merge branch 'refactor'
Diffstat (limited to 'common/rulecheck.cc')
-rw-r--r--common/rulecheck.cc12
1 files changed, 6 insertions, 6 deletions
diff --git a/common/rulecheck.cc b/common/rulecheck.cc
index 987eb602..2f70498f 100644
--- a/common/rulecheck.cc
+++ b/common/rulecheck.cc
@@ -5,13 +5,13 @@
NEXTPNR_NAMESPACE_BEGIN
-bool check_all_nets_driven(Design *design)
+bool check_all_nets_driven(Context *ctx)
{
const bool debug = false;
log_info("Rule checker, Verifying pre-placed design\n");
- for (auto cell_entry : design->cells) {
+ for (auto cell_entry : ctx->cells) {
CellInfo *cell = cell_entry.second;
if (debug)
@@ -37,12 +37,12 @@ bool check_all_nets_driven(Design *design)
if (debug)
log_info(" Checking for a net named \'%s\'\n",
port.net->name.c_str());
- assert(design->nets.count(port.net->name) > 0);
+ assert(ctx->nets.count(port.net->name) > 0);
}
}
}
- for (auto net_entry : design->nets) {
+ for (auto net_entry : ctx->nets) {
NetInfo *net = net_entry.second;
assert(net->name == net_entry.first);
@@ -52,7 +52,7 @@ bool check_all_nets_driven(Design *design)
if (debug)
log_info(" Checking for a driver cell named \'%s\'\n",
net->driver.cell->name.c_str());
- assert(design->cells.count(net->driver.cell->name) > 0);
+ assert(ctx->cells.count(net->driver.cell->name) > 0);
}
for (auto user : net->users) {
@@ -62,7 +62,7 @@ bool check_all_nets_driven(Design *design)
if (debug)
log_info(" Checking for a user cell named \'%s\'\n",
user.cell->name.c_str());
- assert(design->cells.count(user.cell->name) > 0);
+ assert(ctx->cells.count(user.cell->name) > 0);
}
}
}