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| author | Sylvain Munaut <tnt@246tNt.com> | 2018-11-28 10:04:06 +0100 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2018-11-28 16:04:43 +0100 |
| commit | a65b12e8d6d291c04a3982448250014c7de3cbd3 (patch) | |
| tree | 8acf7e344a9531223166e3057aa533f55ff82d32 /bba | |
| parent | 7a2ef27d6c27425bc39ef3a71b0df8b1c608d599 (diff) | |
| download | nextpnr-a65b12e8d6d291c04a3982448250014c7de3cbd3.tar.gz nextpnr-a65b12e8d6d291c04a3982448250014c7de3cbd3.tar.bz2 nextpnr-a65b12e8d6d291c04a3982448250014c7de3cbd3.zip | |
ice40: Revamp the whole PLL placement/validity check logic
We do a pre-pass on all the PLLs to place them before packing.
To place them:
- First pass with all the PADs PLLs since those can only fit at one
specific BEL depending on the input connection
- Second pass with all the dual outputs CORE PLLs. Those can go
anywhere where there is no conflicts with their A & B outputs and
used IO pins
- Third pass with the single output CORE PLLs. Those have the least
constrains.
During theses passes, we also check the validity of all their connections.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'bba')
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