Improving code style and fixing dummy

Signed-off-by: David Shah <davey1576@gmail.com>

5 files changed, 34 insertions, 15 deletions

diff --git a/common/place_sa.cc b/common/place_sa.cc
index a0c32c1d..6012adf8 100644
--- a/common/place_sa.cc
+++ b/common/place_sa.cc
@@ -135,6 +135,7 @@ struct SAState
     bool improved = false;
     int n_move, n_accept;
     int diameter = 35;
+    std::unordered_map<BelType, int> bel_types;
     std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
     std::unordered_set<BelId> locked_bels;
 };
@@ -267,7 +268,6 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
     BelId best_bel = BelId();
     Chip &chip = design->chip;
     BelType targetType = belTypeFromId(cell->type);
-    assert(int(targetType) < state.fast_bels.size());
     int x = 0, y = 0;
     chip.estimatePosition(cell->bel, x, y);
     while (true) {
@@ -275,11 +275,12 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
                                     int(x) + state.diameter + 1);
         int ny = random_int_between(rnd, std::max(int(y) - state.diameter, 0),
                                     int(y) + state.diameter + 1);
-        if (nx >= state.fast_bels.at(int(targetType)).size())
+        int beltype_idx = state.bel_types.at(targetType);
+        if (nx >= state.fast_bels.at(beltype_idx).size())
             continue;
-        if (ny >= state.fast_bels.at(int(targetType)).at(nx).size())
+        if (ny >= state.fast_bels.at(beltype_idx).at(nx).size())
             continue;
-        const auto &fb = state.fast_bels.at(int(targetType)).at(nx).at(ny);
+        const auto &fb = state.fast_bels.at(beltype_idx).at(nx).at(ny);
         if (fb.size() == 0)
             continue;
         BelId bel = fb.at(random_int_between(rnd, 0, fb.size()));
@@ -343,19 +344,27 @@ void place_design_sa(Design *design, int seed)
     }
     // Build up a fast position/type to Bel lookup table
     int max_x = 0, max_y = 0;
+    int bel_types = 0;
     for (auto bel : design->chip.getBels()) {
         int x, y;
         design->chip.estimatePosition(bel, x, y);
         BelType type = design->chip.getBelType(bel);
-        if (state.fast_bels.size() < int(type) + 1)
-            state.fast_bels.resize(int(type) + 1);
-        if (state.fast_bels.at(int(type)).size() < int(x) + 1)
-            state.fast_bels.at(int(type)).resize(int(x) + 1);
-        if (state.fast_bels.at(int(type)).at(int(x)).size() < int(y) + 1)
-            state.fast_bels.at(int(type)).at(int(x)).resize(int(y) + 1);
+        int type_idx;
+        if (state.bel_types.find(type) == state.bel_types.end()) {
+            type_idx = bel_types++;
+            state.bel_types[type] = type_idx;
+        } else {
+            type_idx = state.bel_types.at(type);
+        }
+        if (state.fast_bels.size() < type_idx + 1)
+            state.fast_bels.resize(type_idx + 1);
+        if (state.fast_bels.at(type_idx).size() < int(x) + 1)
+            state.fast_bels.at(type_idx).resize(int(x) + 1);
+        if (state.fast_bels.at(type_idx).at(int(x)).size() < int(y) + 1)
+            state.fast_bels.at(type_idx).at(int(x)).resize(int(y) + 1);
         max_x = std::max(max_x, int(x));
         max_y = std::max(max_y, int(y));
-        state.fast_bels.at(int(type)).at(int(x)).at(int((y))).push_back(bel);
+        state.fast_bels.at(type_idx).at(int(x)).at(int((y))).push_back(bel);
     }
     state.diameter = std::max(max_x, max_y) + 1;
     // Calculate wirelength after initial placement
diff --git a/dummy/arch_place.cc b/dummy/arch_place.cc
index 15f813ae..07ff53ae 100644
--- a/dummy/arch_place.cc
+++ b/dummy/arch_place.cc
@@ -26,4 +26,9 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
     return true;
 }
 
+bool isBelLocationValid(Design *design, BelId bel)
+{
+    return true;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/dummy/arch_place.h b/dummy/arch_place.h
index 66789b7d..1e14ec68 100644
--- a/dummy/arch_place.h
+++ b/dummy/arch_place.h
@@ -31,6 +31,9 @@ NEXTPNR_NAMESPACE_BEGIN
 // such as conflicting set/reset signals, etc
 bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel);
 
+// Return true whether all Bels at a given location are valid
+bool isBelLocationValid(Design *design, BelId bel);
+
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/frontend/json/jsonparse.cc b/frontend/json/jsonparse.cc
index 0b06f980..3c060fd7 100644
--- a/frontend/json/jsonparse.cc
+++ b/frontend/json/jsonparse.cc
@@ -741,9 +741,10 @@ void json_import(Design *design, string modname, JsonNode *node)
                         netnames.resize(netid + 1);
                     netnames.at(netid) =
                             basename +
-                            (num_bits == 1 ? "" : std::string("[") +
-                                                          std::to_string(i) +
-                                                          std::string("]"));
+                            (num_bits == 1
+                                     ? ""
+                                     : std::string("[") + std::to_string(i) +
+                                               std::string("]"));
                 }
             }
         }
diff --git a/ice40/cells.cc b/ice40/cells.cc
index b11a2a77..fb264051 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -147,7 +147,8 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
 
     if (citer != config.end()) {
         if ((config.end() - citer) >= 2) {
-            assert(*(citer++) == 'S');
+            char c = *(citer++);
+            assert(c == 'S');
             lc->params["ASYNC_SR"] = "0";
         } else {
             lc->params["ASYNC_SR"] = "1";