machxo2: Add demo.sh TinyFPGA Ax example.

4 files changed, 50 insertions, 1 deletions

diff --git a/machxo2/examples/.gitignore b/machxo2/examples/.gitignore
index 87d5128b..91167252 100644
--- a/machxo2/examples/.gitignore
+++ b/machxo2/examples/.gitignore
@@ -7,3 +7,5 @@ pack*.v
 place*.v
 pnr*.v
 abc.history
+/tinyfpga.txt
+/tinyfpga.bit
diff --git a/machxo2/examples/README.md b/machxo2/examples/README.md
index e940c01c..bcffeea3 100644
--- a/machxo2/examples/README.md
+++ b/machxo2/examples/README.md
@@ -18,11 +18,16 @@ This contains a simple example of running `nextpnr-machxo2`:
   All possible inputs and resulting outputs can be tested in reasonable time by
   using `yosys`' built-in SAT solver or [`z3`](https://github.com/Z3Prover/z3),
   an external SMT solver.
+* `demo.sh` creates a blinky bitstream for [TinyFPGA Ax](https://tinyfpga.com/a-series-guide.html)
+  and writes the resulting bitstream to MachXO2's internal flash using
+  [`tinyproga`](https://github.com/tinyfpga/TinyFPGA-A-Programmer).
 
 As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`, and
 `mitertest.sh` are subject to change.
 
 ## How To Run
+The following applies to all `sh` scripts except `demo.sh`, which requires no
+arguments.
 
 Each `sh` script runs yosys and nextpnr to validate a blinky design in various
 ways. The `mode` argument to each script- `pack`, `place`, or `pnr`- stop
@@ -37,7 +42,8 @@ SMT solver.
 To keep file count lower, all yosys scripts are written inline inside the
 `sh` scripts using the `-p` option.
 
-To clean output files, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log {pack,place,pnr}*.v blinky_simtest*`
+### Clean
+To clean output files from _all_ scripts, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log tinyfpga.txt tinyfpga.bit {pack,place,pnr}*.v blinky_simtest*`
 
 ## Environment Variables For Scripts
 
@@ -53,3 +59,6 @@ To clean output files, run: `rm -rf *.dot *.json *.png *.vcd *.smt2 *.log {pack,
   returns. You may want to set this to `/path/to/yosys/src/share/machxo2/cells_sim.v`
   if doing development; `yosys-config` cannot find these "before-installation"
   simulation models.
+* `TRELLIS_DB`- Set to the location of the Project Trellis database to use.
+  Defaults to nothing, which means `ecppack` will use whatever database is on
+  its path.
diff --git a/machxo2/examples/demo.sh b/machxo2/examples/demo.sh
new file mode 100644
index 00000000..6979f111
--- /dev/null
+++ b/machxo2/examples/demo.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ ! -z ${TRELLIS_DB+x} ]; then
+    DB_ARG="--db $TRELLIS_DB"
+fi
+
+${YOSYS:-yosys} -p 'synth_machxo2 -json tinyfpga.json' tinyfpga.v
+${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json tinyfpga.json --textcfg tinyfpga.txt
+ecppack --compress $DB_ARG tinyfpga.txt tinyfpga.bit
+tinyproga -b tinyfpga.bit
diff --git a/machxo2/examples/tinyfpga.v b/machxo2/examples/tinyfpga.v
new file mode 100644
index 00000000..dfc2710d
--- /dev/null
+++ b/machxo2/examples/tinyfpga.v
@@ -0,0 +1,28 @@
+// Modified from:
+// https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
+// https://tinyfpga.com/a-series-guide.html used as a basis.
+
+module TinyFPGA_A2 (
+  (* LOC="13" *)
+  inout pin1
+);
+
+
+  wire clk;
+
+  OSCH #(
+    .NOM_FREQ("16.63")
+  ) internal_oscillator_inst (
+    .STDBY(1'b0),
+    .OSC(clk)
+  );
+
+  reg [23:0] led_timer;
+
+  always @(posedge clk) begin
+    led_timer <= led_timer + 1;
+  end
+
+  // left side of board
+  assign pin1 = led_timer[23];
+endmodule