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| author | David Shah <davey1576@gmail.com> | 2018-08-01 10:45:28 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-08-01 10:45:28 +0200 |
| commit | cceda82d40cb3d3a536449b2fa5870a8e355f21b (patch) | |
| tree | 18dae5f69e2b6f34ee693000871783f59f1f26d6 | |
| parent | b17b0680b54c48846701ee344ea558406e73497c (diff) | |
| download | nextpnr-cceda82d40cb3d3a536449b2fa5870a8e355f21b.tar.gz nextpnr-cceda82d40cb3d3a536449b2fa5870a8e355f21b.tar.bz2 nextpnr-cceda82d40cb3d3a536449b2fa5870a8e355f21b.zip | |
More FAQ tweaks
Signed-off-by: David Shah <davey1576@gmail.com>
| -rw-r--r-- | docs/faq.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/faq.md b/docs/faq.md index 6773c594..d842ea2e 100644 --- a/docs/faq.md +++ b/docs/faq.md @@ -49,7 +49,7 @@ Nextpnr and other tools [Verilog to Routing](https://verilogtorouting.org). * If you are developing FPGA code in **Verilog** for a **Lattice iCE40** and - need an open source toolchain, we suggest you use Yosys and nextpnr. + need an open source toolchain, we suggest you use [Yosys](http://www.clifford.at/yosys/) and nextpnr. * If you are developing FPGA code in **Verilog** for a **Lattice iCE40** with Yosys and the **existing Arachne-PNR toolchain**, we suggest you start thinking about @@ -77,10 +77,10 @@ it was never designed to support multiple different FPGA devices, nor more complicated timing driven placement and routing used by most commercial place and route tools. -It felt like extending Arachne-PNR was not going to be the best path forward, so +It felt like extending arachne-pnr was not going to be the best path forward, so it was decided to build nextpnr as replacement. -### Arachne-PNR does X better! +### arachne-pnr does X better! If you have a use case which prevents you from switching to nextpnr from arachne, we want to hear about it! Please create an issue and we will do our best to solve the problem! |